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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8b648e54747sm1400381b3a.11.2026.11.09.06.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 06:21:59 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 13/15] drm/msm/a8xx: Use CP_PROTECT_PIPE regs Date: Mon, 9 Nov 2026 06:19:59 -0800 Message-ID: <20261109142111.256630-14-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261109142111.256630-1-robin.clark@oss.qualcomm.com> References: <20261109142111.256630-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA5MDA1NyBTYWx0ZWRfX1V97Hd3Ars69 sladnn9a/n7o37OgPkt6WDCi4zr2dwdSYllCKFUL+isRx5xi5tOWsSDQmv8cLjaHmbaK26XU3RC 08yVEAz2NCTqzlmuQRHMyZ4Ks22We5xOPiUXT/SRX7zXRX1AIvDxgWSAuocfpHcni2nTZMaJtL4 rRnqG0oItgaRXCBQbr2qSmZHrEQ+q6sIa9xIZgGNV0LaqWeZouRsww7Ms8n9WXl6pNt3FTTbudb I4ZOLnO/6T+MUney7T6e9MFFefoFdnnXDn0/7iGsvuz6XsL5oZJUPoPXhKyMXPRvxSWTGFmUrP3 1HkkTMCQxrlxBx0ZgVYBYUbD+b5PrxK4KBrOEQ5rvrY6CPPjBm+KgB3UhFsEnj42A0KcK5ALYHx qeiTcG65JAz7tf1nUsN6uJKp/wJkzfx1mmr0bIZVJz0Oq1xa3zeHE9Ian7uGvuyDDyK+YZkggwd k+hHDiu9di4S/ljqyqw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA5MDA1NyBTYWx0ZWRfXw8llv9d6MeTI zboASQNNSZpf8t12vtDd+m46KYv7Q8YUQeMyRw31Ir9zNzyqhFx8WczZyqQr/aS1MOGCDhG6yhB s3U/+KsjeMEYFKCU3TzTNrcT/SPIuQ4= X-Proofpoint-ORIG-GUID: FEyma45u9yj6kaJhi9unmpB22iKXSs_Z X-Authority-Analysis: v=2.4 cv=TaQDJhQh c=1 sm=1 tr=0 ts=6af1d709 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=UnxhJFuZtzOLgjs1IeAA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: FEyma45u9yj6kaJhi9unmpB22iKXSs_Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-09_05,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 bulkscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611090057 If there are not enough global CP_PROTECT_GLOBAL regs, we can use CP_PROTECT_PIPE regs for the extra spans. We just need to configure them the same on all pipes. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Konrad Dybcio Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index f65bf82e5c21..f6afa5b3b0bb 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -261,12 +261,21 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) a8xx_aperture_clear(gpu); - for (i = 0; i < protect->count; i++) { + for (i = 0; i < min(64, protect->count); i++) { /* Intentionally skip writing to some registers */ - if (protect->regs[i]) { - gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); - final_cfg = protect->regs[i]; - } + if (!protect->regs[i]) + continue; + gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); + final_cfg = protect->regs[i]; + } + + for (; i < protect->count; i++) { + /* Intentionally skip writing to some registers */ + if (!protect->regs[i]) + continue; + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + final_cfg = protect->regs[i]; } /* -- 2.56.0