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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8b64a1e6232sm1454677b3a.52.2026.11.09.06.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 06:21:27 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 06/15] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Mon, 9 Nov 2026 06:19:52 -0800 Message-ID: <20261109142111.256630-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261109142111.256630-1-robin.clark@oss.qualcomm.com> References: <20261109142111.256630-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA5MDA1NyBTYWx0ZWRfX4u1FcfvBoTcZ VYtqz9o7hq1bEsX+3WobG85ZnCkMHcEhNpsjcXpQtOBspb3m7Fs0ffz3oemBXbwTBYHKIh24hGg omAUfqqquL9MdASg5eYrWfh+VwcYS/s= X-Proofpoint-GUID: oqgutMzhi6X8e5bnahp7jefYQCga7xAb X-Proofpoint-ORIG-GUID: oqgutMzhi6X8e5bnahp7jefYQCga7xAb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA5MDA1NyBTYWx0ZWRfX8y/CrbMvJSSi MrPC022SEaPOJne5+NaQIvoM6HXFqt7rS4xMZwd89MXYGsxJLNN+zrJBKPsLbCELWaNTzRNOCOF YXeax3Rozv2K3INWcGlVxnR9BZZeQ+GQYJCGKT4RGx9o9yEgEXEAwcvlRAtiaRrcezuLanriHnC +QeJWC9fym8vw2nBVB8YrlY7aX1SGZSp3lOUdWkEN1pO5rino8Iwy5XKUFPvfIUAno77YSM6kbe hPEon7U7068ISR2NvqVkONmouoLD1MCBezb8snVjQv0FStUV93gM8l3TCxly02J6HVwd29I/beO ZPrNbwX8rCG4xSzQj0gfeZgExyGP9jOsC5X1ZA6GFGC0KxlyGyQxTmrKJQuxEDTuwy9t2DLLErQ U0ogyYP35TD9KXkQs/78vMJ5Qp/HSMDDhGMbXxA8XHj2md626vHzEY4Yxol5RmUF4qYWvsSnmss 3TU7DpSBvbahxfnIQ1g== X-Authority-Analysis: v=2.4 cv=XuRvqlF9 c=1 sm=1 tr=0 ts=6af1d6e9 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-09_05,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611090057 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Acked-by: Konrad Dybcio Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Akhil P Oommen Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a29f8149493c..59898b49a201 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -373,6 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -392,7 +393,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0