Re: [PATCH v2] spi: intel: only check locked opmenu for SW sequencer operations

[Mika Westerberg <mika.westerberg@linux.intel.com>]

Hi,

On Sun, Nov 08, 2026 at 12:37:28PM -0800, Rosen Penev wrote:
> On controllers that use the software sequencer for register access (LPT
> and BYT), intel_spi_supports_mem_op() rejects any operation whose opcode
> is not in the BIOS-locked OPMENU. However the check is applied to every
> operation, including normal data reads and writes which are always
> executed by the hardware sequencer and never consult the OPMENU.
> 
> On a Dell Precision M4800 (Lynx Point) the BIOS locks OPMENU to
> {02, 3b, 20, 05, 9f, 9f, 00, 00}, which lacks both READ (0x03) and
> FAST_READ (0x0b). As a result every read op is rejected and spi-nor
> fails to probe both flash components:
> 
>   intel-spi intel-spi: 0x3 not supported
>   intel-spi intel-spi: 0xb not supported
>   spi-nor spi0.0: can't select read settings supported by both the SPI controller and memory.
>   spi-nor spi0.0: probe with driver spi-nor failed with error -22
> 
> Only enforce the OPMENU check for operations that actually go through
> the software sequencer: register reads/writes when swseq_reg is set and
> erase when swseq_erase is set.
> 
> Write Enable (0x06) and Write Disable (0x04) are excluded as well, even
> though they are register writes. WREN is never issued from the OPMENU:
> intel_spi_write_reg() verifies it is in PREOP_OPTYPE and uses it as the
> atomic preopcode of the next cycle. WRDI is not sent to the flash at
> all. Rejecting them whenever they are missing from the OPMENU, as on the
> M4800 where 0x06 is only in PREOP_OPTYPE, makes every program and erase
> fail with -EOPNOTSUPP.
> 
> With this both flash chips (W25Q64 and W25Q32) probe and read back
> correctly.
> 
> Fixes: e23e5a05d1fd ("mtd: spi-nor: intel-spi: Convert to SPI MEM")
> Signed-off-by: Rosen Penev <rosenp@gmail.com>

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>