[PATCH 3/3] PCI: Honor window granularity during resource distribution

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

When a bus below a hotplug bridge has BARs smaller than the window
granularity, removing them leaves available[i].start unaligned.
pci_bus_distribute_available_resources() then aligns the start up for the
downstream bridge but keeps the end, so the size passed to
adjust_bridge_window() has a sub-granularity tail. The bridge window ends
up not being a multiple of the window granularity.

Align the size down to the window granularity after aligning the start.

Consider a hotplug Root Port (bus 01) with a Switch Upstream Port (bus 02)
below it that has an e1000 and an ivshmem with a 64k pref BAR as its other
Functions. When the switch is hot-added (emulated with a remove and
rescan), /proc/iomem before and after this change is:

   faa00000-fe9fffff : PCI Bus 0000:01
  -    faa00000-fe8200ff : PCI Bus 0000:02
  +    faa00000-fe7fffff : PCI Bus 0000:02
         faa00000-fc8fffff : PCI Bus 0000:03
           faa00000-faa000ff : 0000:03:00.0
         fc900000-fe6fffff : PCI Bus 0000:04
  -    fe820100-fe8201ff : 0000:01:00.2
  -    fe840000-fe85ffff : 0000:01:00.1
  +    fe800000-fe81ffff : 0000:01:00.1
  +    fe820000-fe8200ff : 0000:01:00.2
  ...
     100000000-13fffffff : PCI Bus 0000:01
  -    100000000-12000ffff : PCI Bus 0000:02
  +    100000000-11fffffff : PCI Bus 0000:02
         100000000-10fffffff : PCI Bus 0000:03
           100000000-10fffffff : 0000:03:00.0
         110000000-117ffffff : PCI Bus 0000:04
  -    120010000-12001ffff : 0000:01:00.2
  +    120000000-12000ffff : 0000:01:00.2

Before, the bus 02 windows end at fe8200ff and 12000ffff, which are not 1M
aligned and thus impossible for a bridge window. As such an end cannot be
written to the bridge, the resource tree does not match what the bridge
actually uses: it decodes up to fe8fffff and 1200fffff, covering the BARs
of 01:00.1 and 01:00.2.

Fixes: 9db0b9b6a142 ("PCI: Take other bus devices into account when distributing resources")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Cc: stable@vger.kernel.org
---
 drivers/pci/setup-bus.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 9d8b22d1e6ad..5651966f3029 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1974,7 +1974,7 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
 	unsigned int normal_bridges = 0, hotplug_bridges = 0;
 	struct pci_dev *dev, *bridge = bus->self;
 	resource_size_t per_bridge[PCI_P2P_BRIDGE_RESOURCE_NUM];
-	resource_size_t align;
+	resource_size_t align, win_align;
 	int i;
 
 	for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) {
@@ -1989,10 +1989,22 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
 		 * window.
 		 */
 		align = pci_resource_alignment(bridge, res);
-		if (!resource_assigned(res) && align)
+		if (!resource_assigned(res) && align) {
 			available[i].start = min(ALIGN(available[i].start, align),
 						 available[i].end + 1);
 
+			/*
+			 * Small BARs on the parent bus may result in a
+			 * size that is not a multiple of the window
+			 * granularity (usually 1M), which is impossible
+			 * for a bridge window.
+			 */
+			win_align = pci_min_window_alignment(bus, res->flags);
+			resource_set_size(&available[i],
+					  ALIGN_DOWN(resource_size(&available[i]),
+						     win_align));
+		}
+
 		/*
 		 * Now that we have adjusted for alignment, update the
 		 * bridge window resources to fill as much remaining
-- 
2.47.3