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Mon, 09 Nov 2026 07:45:04 -0800 (PST) Received: from hp-z640.fritz.box ([51.37.204.122]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b7e32ad4d1sm257163645e9.5.2026.11.09.07.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 07:45:03 -0800 (PST) From: Owen O'Hehir To: Alexandre Belloni , linux-rtc@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , "ziv.xu" , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , E Shattow Subject: [PATCH v3 0/4] rtc: Add StarFive JH7110 RTC support Date: Mon, 9 Nov 2026 15:44:57 +0000 Message-ID: <20261109154501.63762-1-oo.hehir@gmail.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The JH7110 has an RTC in its always-on domain that mainline does not support. This series adds a binding, a driver, a MAINTAINERS entry and the SoC DT node. The driver is based on the StarFive vendor driver (rtc-starfive.c, commit ebac2b5 in the StarFive 6.12 tree), reworked for mainline: - hardware calibration and the default time set in probe are dropped - wakeup uses the generic wake IRQ helpers instead of the irq_desc hack - set_time waits for the counter to load the new time - read_time re-reads if the time rolls over between TIME and DATE - the offset rounds to the nearest step and follows the sysfs sign convention (positive = slower) - the 32.768 kHz counter clock is described in the binding and enabled Thanks to ziv.xu and Hal Feng at StarFive for the original driver. Tested on a VisionFive 2 v1.3B with next-20261105 and v7.3.1: setting and reading the time across the 2000-2099 range (out-of-range years refused), leap day and century rollover, the alarm interrupt with cancel, the offset, the rate over 60 s, and setting the system clock at boot. Not tested: suspend wakeup, drift over hours, and keeping time across a power-off, as the board has no RTC battery connector. Known behaviour: the RTC loses about the length of a reboot across a warm reboot; the counter appears to stop during reset. After the StarFive vendor kernel the first boot found an invalid time. I would appreciate an opinion on whether this is expected of the hardware or something the driver should handle. Changes in v3: - dt-bindings: add Conor's Acked-by - driver: add my copyright line; drop the extra space before the register bit field defines (as requested by E Shattow) - dts: rename the node label from rtc to soc_rtc, leaving rtc free for a carrier board's RTC (as requested by E Shattow) Changes in v2: - dt-bindings: list myself as maintainer instead of the RTC subsystem maintainer (as requested by Conor) - MAINTAINERS: new patch adding an entry for the driver & binding - driver: drop the include (as requested by Uwe) v1: https://lore.kernel.org/r/20261106175600.3877614-0-oo.hehir@gmail.com v2: https://lore.kernel.org/r/20261108212826.15890-1-oo.hehir@gmail.com Owen O'Hehir (3): dt-bindings: rtc: Add StarFive JH7110 RTC MAINTAINERS: Add entry for the StarFive JH7110 RTC driver riscv: dts: starfive: jh7110: Add the RTC node ziv.xu (1): rtc: Add StarFive JH7110 RTC driver .../bindings/rtc/starfive,jh7110-rtc.yaml | 85 +++++ MAINTAINERS | 7 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 + drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-jh7110.c | 324 ++++++++++++++++++ 6 files changed, 442 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml create mode 100644 drivers/rtc/rtc-jh7110.c base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b -- 2.43.0