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[2003:e3:7f3a:b7a3:62bc:cef4:3315:8012]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4974b7645cesm4574346f8f.32.2026.11.09.08.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 08:55:47 -0800 (PST) From: Javid Rzayev To: ricardo.neri-calderon@linux.intel.com Cc: darwi@linutronix.de, kprateek.nayak@amd.com, len.brown@intel.com, linux-kernel@vger.kernel.org, ricardo.neri@intel.com Subject: Re: [PATCH RFC] x86/cacheinfo: Remove get_cache_id() due to ID collisions Date: Mon, 9 Nov 2026 17:55:37 +0100 Message-ID: <20261109165537.6656-1-rz.cavid@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260319-rneri-x86-cacheinfoid-bug-v1-1-5875849dd0e5@linux.intel.com> References: <20260319-rneri-x86-cacheinfoid-bug-v1-1-5875849dd0e5@linux.intel.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Thu, Mar 19, 2026 at 05:38:00AM -0700, Ricardo Neri wrote: > calc_cache_topo_id() and get_cache_id() both compute cache IDs used to > determine which CPUs share a cache. Intel processors use > calc_cache_topo_id(), while Hygon and recent AMD processors use > get_cache_id(). Intel processors use get_cache_id() as well, but only to > populate /sys/devices/system/cpu/cpuN/cache/index*/id. Hi Ricardo, On Intel hybrid parts the bad IDs do not stay confined to cache/index*/id: after CPU hotplug they leak into shared_cpu_list. I hit the collision on Arrow Lake-S (Core Ultra 7 265, 8P+12E, no SMT). Even without SMT, CPUID leaf 4 on the P-cores reports 2 threads sharing L1, so get_cache_id() shifts P-core APIC IDs by 1 and E-core APIC IDs by 0: CPU type APICID L1 id (unpatched) 4 P 0x30 0x18 8 E 0x18 0x18 <- collides with CPU4 5 P 0x38 0x1c 10 E 0x1c 0x1c <- collides with CPU5 When a CPU goes offline, cache_shared_cpu_map_remove() clears cpu_map_populated. When it comes back online, the LLC is still valid, so x86 populate_cache_leaves() is skipped and the generic cache_shared_cpu_map_setup() rebuilds the maps by comparing ci->id. On v7.4-rc2 (unpatched), right after boot L1 shared_cpu_list is correct (cpu4: "4", cpu8: "8") and only the IDs collide. After offlining and onlining cpu8 it becomes "4,8" for both CPUs, i.e. a P-core and an E-core appear to share L1. On a distro 6.12 kernel, after several suspend/resume cycles both pairs (4,8 and 5,10) were wrong. With this patch applied on v7.4-rc2, L1 IDs equal the APIC IDs and are unique. Offlining/onlining cpu8 and cpu10 leaves all shared_cpu_lists intact. L2 IDs change (e.g. 0x3 -> 0x18 for the cluster of CPUs 8-11) but the shared_cpu_lists are unchanged. It may be worth mentioning the hotplug effect in the changelog. Do you plan to post a non-RFC version to the x86 maintainers? Tested-by: Javid Rzayev Thanks, Javid