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From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: macro@orcam.me.uk, Florian Fainelli <f.fainelli@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Thomas Gleixner <tglx@kernel.org>,
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2] MIPS: SiByte: Update effective IRQ affinity
Date: Mon,  9 Nov 2026 10:26:22 -0800	[thread overview]
Message-ID: <20261109182627.3517986-1-f.fainelli@gmail.com> (raw)

Booting an SB1250 kernel with CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
enabled reports:

  genirq: irq_chip SB1250-IMR did not update eff. affinity mask of irq 2

The interrupt mapper selects the first online CPU in the requested mask,
but sb1250_set_affinity() does not update the effective affinity mask.
Returning IRQ_SET_MASK_OK makes the IRQ core copy the requested mask to
irq_common_data.affinity, but leaves the separate effective affinity mask
empty, triggering irq_validate_effective_affinity().

Update the effective affinity with the single logical CPU selected as
the hardware target. Apply the same update to the analogous BCM1480
callback, and use IRQ_SET_MASK_OK explicitly in both callbacks.

The IRQ core already rejects masks without an online CPU for normal
affinity changes, so no additional mask validation is needed here.

Fixes: 421d1563c662 ("mips: Validate online cpus in irq_set_affinity() callbacks")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
Changes in v2:

- update commit message
- cover bcm1480, remove the check on nr_cpu_ids

 arch/mips/sibyte/bcm1480/irq.c | 3 ++-
 arch/mips/sibyte/sb1250/irq.c  | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 7929bee911eb..4c18a2c755d2 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -113,9 +113,10 @@ static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask,
 			____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 		}
 	}
+	irq_data_update_effective_affinity(d, cpumask_of(i));
 	raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 
-	return 0;
+	return IRQ_SET_MASK_OK;
 }
 #endif
 
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index d7a656cd7ec0..a971bdfac356 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -108,7 +108,7 @@ static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
 	irq_data_update_effective_affinity(d, cpumask_of(i));
 	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 
-	return 0;
+	return IRQ_SET_MASK_OK;
 }
 #endif
 
-- 
2.53.0


                 reply	other threads:[~2026-11-09 18:26 UTC|newest]

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