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charset="utf-8" Message-Id: <20261110-cv75-gpio-v14-11-e586aad0467a@ambarella.com> References: <20261110-cv75-gpio-v14-0-e586aad0467a@ambarella.com> In-Reply-To: <20261110-cv75-gpio-v14-0-e586aad0467a@ambarella.com> To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , Mika Westerberg , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794285162; l=4176; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=7PBsQ7BHt0WowwsQlVwR3GG8j78Lnd2HAGKwF7XYLks=; b=7NNUNZi+Y0ialnXX8hIEy01mHK1NzABGKvCh4HcFg3rjk324TAq1dKiZVOlmmHZZoGagrl1+5 AYSx0B6djiqBSlb9Sr+Uk0yYlpeQDf1Vq4mKzv17b5eJV/eYDOmbcIZ X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com Content-Transfer-Encoding: 7bit From: Long Zhao Add a 32-bit, 32-line layout with DAT/DIR/IS/IBE/IEV/IE/MIS/IC plus MASK and ENABLE. Probe unmasks the bank and enables the controller. IRQ type changes also clear the pending bit. This derivative does not need write-after-direction or system suspend save/restore. Cache DAT (REGCACHE_FLAT_S, not volatile) so gpio_set() updates one bit from the output shadow instead of read-modify-writing the pin level across the bank. Match the part with designer AMBA_VENDOR_AMBARELLA (JEP106 identity 0x68, bit 7 set) and part number 0x061. Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/amba/bus.h | 1 + 2 files changed, 59 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index cb1ef0f3774c..ff9215447bbb 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -39,6 +39,18 @@ #define PL061_GPIO_NR 8 #define PL061_DATA_OFFSET 2 +#define AMBARELLA_GPIO_NR 32 +#define AMBARELLA_DAT 0x00 +#define AMBARELLA_DIR 0x04 +#define AMBARELLA_IS 0x08 +#define AMBARELLA_IBE 0x0c +#define AMBARELLA_IEV 0x10 +#define AMBARELLA_IE 0x14 +#define AMBARELLA_MIS 0x20 +#define AMBARELLA_IC 0x24 +#define AMBARELLA_MASK 0x28 +#define AMBARELLA_ENABLE 0x2c + struct pl061_regs { unsigned int dat; unsigned int dir; @@ -93,6 +105,17 @@ static bool pl061_arm_volatile_reg(struct device *dev, unsigned int reg) } } +static bool pl061_ambarella_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AMBARELLA_MIS: + case AMBARELLA_IC: + return true; + default: + return false; + } +} + static const struct regmap_config pl061_arm_regmap_config = { .reg_bits = 16, .val_bits = 8, @@ -103,6 +126,16 @@ static const struct regmap_config pl061_arm_regmap_config = { .use_raw_spinlock = true, }; +static const struct regmap_config pl061_ambarella_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = AMBARELLA_ENABLE, + .volatile_reg = pl061_ambarella_volatile_reg, + .cache_type = REGCACHE_FLAT_S, + .use_raw_spinlock = true, +}; + static unsigned int pl061_line_mask(struct pl061 *pl061, irq_hw_number_t hwirq) { return BIT(hwirq % pl061->data->ngpio); @@ -336,6 +369,19 @@ static const struct pl061_regs pl061_arm_regs = { .ic = GPIOIC, }; +static const struct pl061_regs pl061_ambarella_regs = { + .dat = AMBARELLA_DAT, + .dir = AMBARELLA_DIR, + .is = AMBARELLA_IS, + .ibe = AMBARELLA_IBE, + .iev = AMBARELLA_IEV, + .ie = AMBARELLA_IE, + .mis = AMBARELLA_MIS, + .ic = AMBARELLA_IC, + .mask = AMBARELLA_MASK, + .enable = AMBARELLA_ENABLE, +}; + static const struct pl061_drvdata pl061_arm = { .regmap_config = &pl061_arm_regmap_config, .regs = &pl061_arm_regs, @@ -345,6 +391,13 @@ static const struct pl061_drvdata pl061_arm = { .reg_mask_xlate = pl061_arm_reg_mask_xlate, }; +static const struct pl061_drvdata pl061_ambarella = { + .regmap_config = &pl061_ambarella_regmap_config, + .regs = &pl061_ambarella_regs, + .ngpio = AMBARELLA_GPIO_NR, + .clear_irq_on_type = true, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct gpio_regmap_config config = {}; @@ -521,6 +574,11 @@ static const struct amba_id pl061_ids[] = { .mask = 0x000fffff, .data = (void *)&pl061_arm, }, + { + .id = (AMBA_VENDOR_AMBARELLA << 12) | 0x061, + .mask = 0x000fffff, + .data = (void *)&pl061_ambarella, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl061_ids); diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 80a74cd2da7e..411533bfa61d 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -98,6 +98,7 @@ enum amba_vendor { AMBA_VENDOR_ST = 0x80, AMBA_VENDOR_QCOM = 0x51, AMBA_VENDOR_LSI = 0xb6, + AMBA_VENDOR_AMBARELLA = 0xe8, }; extern const struct bus_type amba_bustype; -- 2.34.1