[PATCH 2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate

[Arun Iyengar via B4 Relay <devnull+aiyengar1990.gmail.com@kernel.org>]

From: Arun Iyengar <aiyengar1990@gmail.com>

sun4i-spdif asks for 22.5792 or 24.576 MHz on the S/PDIF (OWA) module
clock, depending on the sample rate family. The spdif clock has no
CLK_SET_RATE_PARENT, so it can only divide down the rate pll-audio
already runs at. Unless another audio device has already set the PLL for
the right family, the power-of-two divider rounds down and the request
succeeds at a wrong rate: about 12.3 MHz from the reset PLL value, so
48 kHz content is sent at about 24 kHz.

Propagate rate changes to the parent, like the audio codec clocks
already do. This is the same change as the one just applied for the H6
[1].

Link: https://lore.kernel.org/all/20261104185027.883011-1-jernej.skrabec@gmail.com/ [1]
Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 CCU")
Cc: stable@vger.kernel.org
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
index d2625fec651a..f703d690a563 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -529,7 +529,7 @@ static struct ccu_div spdif_clk = {
 		.hw.init	= CLK_HW_INIT_PARENTS("spdif",
 						      audio_parents,
 						      &ccu_div_ops,
-						      0),
+						      CLK_SET_RATE_PARENT),
 	},
 };
 

-- 
2.55.0