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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9479e73b2d2sm138653985a.10.2026.11.09.20.55.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:55:43 -0800 (PST) From: Yongxing Mou Date: Tue, 10 Nov 2026 12:54:35 +0800 Subject: [PATCH v8 14/29] drm/msm/dpu: pass msm_display_info to dpu_encoder_get_intf() X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261110-msm-dp-mst-v8-14-d040fb33db5f@oss.qualcomm.com> References: <20261110-msm-dp-mst-v8-0-d040fb33db5f@oss.qualcomm.com> In-Reply-To: <20261110-msm-dp-mst-v8-0-d040fb33db5f@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794286469; l=1951; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=kSG1AwjhdD6UXXB/LAoKM+KcPZ/iXxLYW1hElXuN5Nc=; b=1Ahcc+eArGXWKK2CYbauZTCiZtd9bFfI6sItHoIq65yoqCvQ9mfGCoCrQeVFNLgJuKNWpVsCW PJy5zw+3G1uB3vk13q6TkD4K+aY3gUEiJW1Dvu9X8fj5+CwTAmVwwwn X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=TMjQ2Fla c=1 sm=1 tr=0 ts=6af2a3d0 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=TTd-C8IxYANZTSfMnlIA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEwMDAxOSBTYWx0ZWRfX1hSWWX1A6b1U yHu8Z6dulzJxySjWO/05HqI9tb/fwXVQcZw+X90yC/hu3eKPA+4ERiJb5uYpbZ19EQ5ATLSD6RB XM0e5Cn7ebEkXJwge/vdIjoP8Vng/UyE2aCEeOI4HOMYw83SdZ2I9z/ADxadqPgqZLhVDFRuX0I umQoTAVyUzxa2s/hELOy4C3EhwxJ7Gs5cdV9bcu4yKYI13g2QZ52jRvorhdWb4IAAJ4UrNEH2bL dyR1gnMOko4wQfRYB5YRS8UBXxm1koqD/wD4jJG4YohA63g6fG6+DIWbraW0XXaRFlhWUSCJRQo WQMltGaVHAnzd2BcdZebQO+uUafXsGSBW5n8mU+Gn7vTxaAxldKi4F+UoQjiUU5ysbsIF+8h05C I9EOvxyqKDZ6OF3Gnw46S0C9Mq2BYf11ykQsE58ObqQfVjtgAodYqhiNzy1q/Vj9IWAxFH53SJe Samb3gnXlSu9iiYlDMQ== X-Proofpoint-GUID: 9czb0ONoo1QLJbQG0i_W_mB6oUR0zdJu X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEwMDAxOSBTYWx0ZWRfX8WTOR7E9H1Tt TbKHTZT7DM2BqZYp4zK8flfxPXoRMqzbPjYIbJDwPgGVZ9/w/wOgf4deMWtwzLbypXrwP8iN4fg O0OCg/Eh4uQeu4wHibaYAAzl8h4l2e8= X-Proofpoint-ORIG-GUID: 9czb0ONoo1QLJbQG0i_W_mB6oUR0zdJu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-10_02,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611100019 Derive the controller ID from disp_info->h_tile_instance[index] instead of passing it separately to dpu_encoder_get_intf(). This removes a redundant argument and keeps all interface selection parameters in msm_display_info. No functional change. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 0a6be69a3e83..5e1c98371181 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1435,15 +1435,16 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, struct dpu_rm *dpu_rm, - enum dpu_intf_type type, u32 controller_id) + struct msm_display_info *disp_info, int index) { int i = 0; + u32 controller_id = disp_info->h_tile_instance[index]; - if (type == INTF_WB) + if (disp_info->intf_type == INTF_WB) return NULL; for (i = 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type == type + if (catalog->intf[i].type == disp_info->intf_type && catalog->intf[i].controller_id == controller_id) { return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); } @@ -2672,8 +2673,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, i, controller_id, phys_params.split_role); phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, - disp_info->intf_type, - controller_id); + disp_info, i); if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); -- 2.43.0