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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9479e73b2d2sm138653985a.10.2026.11.09.20.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:56:30 -0800 (PST) From: Yongxing Mou Date: Tue, 10 Nov 2026 12:54:45 +0800 Subject: [PATCH v8 24/29] drm/msm/dp: enable MST on capable sinks X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261110-msm-dp-mst-v8-24-d040fb33db5f@oss.qualcomm.com> References: <20261110-msm-dp-mst-v8-0-d040fb33db5f@oss.qualcomm.com> In-Reply-To: <20261110-msm-dp-mst-v8-0-d040fb33db5f@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794286469; l=5632; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=MQxn5IlgLyQD5lvs7GYrzOJlBKGomT/Bam5EUTVFUfc=; b=pqZSBqM/KXCOlw4EjXksUQ8SdzCIZAWlXsfM3ImxYIWXm1ATC+5t66RSCeWSpx6vnuvWSxaH/ QfCGsnw83EjAGn6V54d2TbYTDqyKSseO5tNPNy7IYCSXN2wLr/pN24U X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: Eyy9Xh5LsdVRHh6R3Yilz_2sqeuam-Lk X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEwMDAxOSBTYWx0ZWRfXznqkWC8HX59o tdls/rf4RFASxFJbOBFgd1vz/6OrX6hJa7A5E1DdujmZJPAnbs54poBc9VwpVACzuIPPE6R/M0D iPx2JqNAet8c8+ydW/u0PreCscl8E/g= X-Authority-Analysis: v=2.4 cv=TOrQ2Fla c=1 sm=1 tr=0 ts=6af2a3ff cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=-w6CXN-5EBmt9i3D_LUA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: Eyy9Xh5LsdVRHh6R3Yilz_2sqeuam-Lk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEwMDAxOSBTYWx0ZWRfXwZgFW3HmVOq5 rzXfVB7t3fUQEXZYqhTFuguChACTTMSmRUjQ+3IMT1ZseJMtGYP7zl5rTp6s6vIRWwWw1sd0f6K R33Xg8GFAQcgO3F/DHN+Z5gO+FrPR6I4BE/pAnCqI6kfvt+UM2NtZHXjV18ksEtYggll86pXfXf PovVjZ3aRRCZBrV2Rz4k4hb9VvARWKXsgHoYj/ReX9mOaDR1uOANKl5P77R7mNIuKL+BjDBgs57 Y0uMf3x/yh80MB1oT04gpqhkWlnQEgk8Xs3tLicRiTrSAFym9r1N8flctrCKkcrIfRmQfnPYunF tWXYlV5EhZjHLa8dNnVDIS0ITH/TonwBKPB1RrqD5xoyyZQbfXJEG+PJCxDE9INd/n4e+5TdTWX 5uBz9r2nJXIpvnF2U8mq3eNYq1NikS7RU2XZXHzrgeNkE9S8pHqBLnG1mxEqUkJBhI2uTNlLggQ z3rS+yV8DSSJ8RH+aWg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-10_02,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611100019 From: Abhinav Kumar MST topology discovery requires the sink to operate in MST mode. Enable MST on sinks that advertise MST capability and are connected to a multi-stream capable DP controller. Once MST is enabled, downstream sink discovery and EDID retrieval are handled through the MST topology rather than the primary DP connector. Activate the MST topology manager on connect and disable it on disconnect to track the sink topology lifecycle. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 52 ++++++++++++++++++++++++++++++++----- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 15 +++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 3 files changed, 61 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index f87eea19c4f5..eeb0e0494900 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -270,10 +271,34 @@ static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd return lttpr_count; } +static void msm_dp_display_mst_enable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp = &dp->msm_dp_display; + int ret; + + /* Clear any pre-existing MST state before enabling MST. */ + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, 0); + if (ret < 0) { + DRM_ERROR("failed to clear DP_MSTM_CTRL, ret=%d\n", ret); + return; + } + + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink MST enablement failed\n"); + return; + } + + msm_dp->mst_active = true; + msm_dp_mst_display_set_mgr_state(msm_dp, true); +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) { struct drm_connector *connector = dp->msm_dp_display.connector; const struct drm_display_info *info = &connector->display_info; + enum drm_dp_mst_mode mst_mode = DRM_DP_SST; int rc = 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; const struct drm_edid *drm_edid = NULL; @@ -288,14 +313,19 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) if (rc) goto end; - drm_edid = drm_edid_read_ddc(connector, &dp->aux->ddc); - drm_edid_connector_update(connector, drm_edid); + if (msm_dp_ctrl_get_stream_cnt(dp->ctrl) > 1) + mst_mode = drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd); - if (!drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(dp->aux)) - return -ETIMEDOUT; + if (mst_mode != DRM_DP_MST) { + drm_edid = drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } } msm_dp_link_process_request(dp->link); @@ -317,6 +347,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) */ msm_dp_link_psm_config(dp->link, &dp->link->link_caps, false); + if (mst_mode == DRM_DP_MST) + msm_dp_display_mst_enable(dp); + msm_dp_link_reset_phy_params_vx_px(dp->link); end: @@ -502,6 +535,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active = false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c index 15405080107f..2b96e003225d 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -362,6 +362,21 @@ int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stream_id, return 0; } +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + int rc; + + rc = drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + drm_err(dp_display->drm_dev, + "[MST] failed to set topology mgr state to %d rc:%d\n", state, rc); + } + + drm_dbg_kms(dp_display->drm_dev, "[MST] set_mgr_state state:%d\n", state); + return rc; +} + void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) { int rc; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/dp_mst_drm.h index 3bd3e66b4eac..84de7ca0c689 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -12,6 +12,7 @@ int msm_dp_mst_mgr_init(struct msm_dp *dp_display, struct msm_dp_link *link, void msm_dp_mst_mgr_destroy(struct msm_dp *dp_display); int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stream_id, struct drm_encoder *encoder); +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state); void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display); #endif /* _DP_MST_DRM_H_ */ -- 2.43.0