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They are submitted separately as they do not depend on the command queue work, and are valuable on their own. A few preparatory patches are also introduced to smoothen the transition. Patches 1 to 7 make the generic bootloader its own type, usable with any DMEM descriptor and not just FWSEC's, and place it at the top of IMEM as reported by the HWCFG register instead of assuming a 64 KiB IMEM. Patch 6 is a bit of an outlier as it allows register array locations to be copied, in order to simplify patch 7 which makes sure the generic bootloader can be used with the r000 boot protocol. Patches 9 to 12 let falcon DMA transfers read from a framebuffer address and tag DMEM blocks, check the per-block offsets for overflow, and simplify the DMA setup flow. The new DMA capabilities remain unused until the r000 load-and-execute handlers land. Based on `drm-rust-next`, tested with TU106 and GA107 using both the 570.144 and 615.71.09 firmware images. [1] https://lore.kernel.org/20260918010719.1176945-1-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot --- Changes in v3: - Perform `imem_dst_start` computation in `GenericBootloader::run` to avoid requiring a `Falcon` parameter in the constructor. (Eliot) - Remove unneeded `ctx_dma` accessor. (Eliot) - Inline `RegisterArrayLoc::clone`. (Sashiko) - Avoid double-read of register in `with_fbif_transcfg`. (Eliot) - Rename `dma_end` to more consistent `end_offset`. (Eliot) - Simplify `dma_wr`. (Eliot) - Link to v2: https://patch.msgid.link/20261107-r000-fw-v2-0-fb37cc5b20cd@nvidia.com Changes in v2: - Remove `Assisted-by: LLM` tags. - Widen the `IMEMC::offs` field to 24 bits to be able to load the bootloader even if IMEM is larger than 64KB. (Eliot) - Accept unbound `Device` to create the generic bootloader. (Eliot) - Fix documentation for GenericBootloader::new and FwsecFirmwareWithBl::new. (Eliot) - Program `FBIF_TRANSCFG` from `GenericBootloader::run`. (Eliot) - Bring `with_fbif_transcfg()` from the later r000 patches. - Use the source offset as tag for tagged DMEM transfers. (Eliot, Sashiko) - Set the `DMTAG` attribute from `with_falcon_mem`. (Eliot) - Program the FBIF_TRANSCFG register in dma_wr. (Eliot) - Link to v1: https://patch.msgid.link/20261103-r000-fw-v1-0-e3d38fc130e3@nvidia.com Changes since John's v3: - Split the IMEM placement change out of the bootloader extraction. - Keep the DMEM descriptor fields private behind a constructor. - Replace the exported bootloader pairing type with a `run()` method. - Make `dma_wr()` able to work with different sources instead of adding a second DMA method. - Split the DMEM tagging and overflow checks into their own patches. --- Alexandre Courbot (7): gpu: nova-core: falcon: widen the IMEM PIO offset to 24 bits rust: io: register: implement Copy and Clone for RegisterArrayLoc gpu: nova-core: falcon: rename the local variables of dma_wr() gpu: nova-core: falcon: allow DMEM DMA transfers to request tagging gpu: nova-core: falcon: allow DMA transfers to read from a framebuffer address gpu: nova-core: falcon: use src_start as FB offset for all DMA transfers gpu: nova-core: falcon: program the FBIF_TRANSCFG register in dma_wr John Hubbard (6): gpu: nova-core: separate the generic falcon bootloader from FWSEC gpu: nova-core: move the bootloader DMEM descriptor out of FWSEC gpu: nova-core: run the generic bootloader from its own type gpu: nova-core: place the generic bootloader at the top of IMEM gpu: nova-core: falcon: introduce and use with_fbif_transcfg gpu: nova-core: falcon: check the per-block DMA offsets for overflow drivers/gpu/nova-core/falcon.rs | 134 +++++++--- drivers/gpu/nova-core/firmware.rs | 1 + drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 215 ++-------------- drivers/gpu/nova-core/firmware/gen_bootloader.rs | 280 +++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 13 +- rust/kernel/io/register.rs | 9 + 6 files changed, 422 insertions(+), 230 deletions(-) --- base-commit: a7cdb17ca0d7ce67e9f3a52d39edd60f03223729 change-id: 20261103-r000-fw-088d39a643b7 Best regards, -- Alexandre Courbot