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The two additions were plain, so a source or destination offset near the top of the 32-bit range would have wrapped or panicked rather than failing the transfer. Add the two with checked arithmetic and fail the transfer with EOVERFLOW when a sum does not fit. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney [acourbot: split out of the DMA helper patch of v3.] Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index a7e41e282ec2..beac0b7ac57e 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -609,12 +609,12 @@ fn dma_wr( // Perform a transfer of size `DMA_LEN`. self.pfalcon.write_reg( regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed() - .try_with_offs(load_offsets.dst_start + pos)?, + .try_with_offs(load_offsets.dst_start.checked_add(pos).ok_or(EOVERFLOW)?)?, ); // The source offset doubles as the virtual address tag for IMEM and tagged DMEM. self.pfalcon.write_reg( regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed() - .with_offs(load_offsets.src_start + pos), + .with_offs(load_offsets.src_start.checked_add(pos).ok_or(EOVERFLOW)?), ); self.pfalcon.write_reg(cmd); -- 2.56.0