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Do it so the caller does not need to program this register beforehand, which could leave the door open to bogus setups. Suggested-by: Eliot Courtney Link: https://lore.kernel.org/all/DMNWO08EFJD8.D2G9X082FUKN@nvidia.com/ Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index beac0b7ac57e..fb4f1cad867e 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -566,7 +566,7 @@ fn dma_wr( // need to perform. let num_transfers = load_offsets.len.div_ceil(DMA_LEN); - let dma_base = match src { + let (dma_base, fbif_target) = match src { FalconDmaSource::Sysmem(dma_obj) => { // Upper limit of transfer is `(num_transfers * DMA_LEN) + load_offsets.src_start`. let end_offset = num_transfers @@ -575,9 +575,12 @@ fn dma_wr( .map(usize::from_safe_cast) .ok_or(EOVERFLOW)?; - io_project!(dma_obj, [try: 0..end_offset]).dma_address() + ( + io_project!(dma_obj, [try: 0..end_offset]).dma_address(), + FalconFbifTarget::CoherentSysmem, + ) } - FalconDmaSource::Framebuffer { base } => base, + FalconDmaSource::Framebuffer { base } => (base, FalconFbifTarget::LocalFb), }; if dma_base % DmaAddress::from(DMA_LEN) > 0 { @@ -605,6 +608,12 @@ fn dma_wr( .with_size(DmaTrfCmdSize::Size256B) .with_falcon_mem(target_mem); + self.pfalcon + .update(regs::NV_PFALCON_FBIF_TRANSCFG::at(0), |v| { + v.with_target(fbif_target) + .with_mem_type(FalconFbifMemType::Physical) + }); + for pos in (0..num_transfers).map(|i| i * DMA_LEN) { // Perform a transfer of size `DMA_LEN`. self.pfalcon.write_reg( @@ -655,11 +664,6 @@ fn dma_load + FalconDmaLoadable>(&self, fw: &F) -> }; self.dma_reset(); - self.pfalcon - .update(regs::NV_PFALCON_FBIF_TRANSCFG::at(0), |v| { - v.with_target(FalconFbifTarget::CoherentSysmem) - .with_mem_type(FalconFbifMemType::Physical) - }); self.dma_wr( FalconDmaSource::Sysmem(&dma_obj), -- 2.56.0