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Nova declared it as 16 bits and carried IMEM PIO destinations as `u16`, which prevents loading anything above 64 KiB of IMEM, a scenario that becomes possible once the generic bootloader is placed at the top of IMEM. Widen the register field and carry the destination as a 24-bit `Bounded`. Suggested-by: Eliot Courtney Link: https://lore.kernel.org/all/DMNAN7KX22SC.QQ5HURCU332A@nvidia.com/ Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 10 +++++++--- drivers/gpu/nova-core/firmware/gen_bootloader.rs | 8 ++++++-- drivers/gpu/nova-core/regs.rs | 2 +- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 0b377bd6524a..a34748abc74a 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -18,6 +18,10 @@ Io, Mmio, // }, + num::{ + Bounded, + TryIntoBounded, // + }, prelude::*, sizes::SZ_4K, time::Delta, @@ -230,13 +234,13 @@ fn try_as_pio_loadable(&self) -> Result> { let end = start + usize::from_safe_cast(params.len); let data = self.as_slice().get(start..end).ok_or(EINVAL)?; - let dst_start = u16::try_from(params.dst_start).map_err(|_| EINVAL)?; + let dst_start = params.dst_start.try_into_bounded().ok_or(EINVAL)?; Ok::<_, Error>(FalconPioImemLoadTarget { data, dst_start, secure, - start_tag: dst_start >> 8, + start_tag: dst_start.shr::<8, 16>().into(), }) }; @@ -272,7 +276,7 @@ fn try_as_pio_loadable(&self) -> Result> { #[derive(Clone)] pub(crate) struct FalconPioImemLoadTarget<'a> { pub(crate) data: &'a [u8], - pub(crate) dst_start: u16, + pub(crate) dst_start: Bounded, pub(crate) secure: bool, pub(crate) start_tag: u16, } diff --git a/drivers/gpu/nova-core/firmware/gen_bootloader.rs b/drivers/gpu/nova-core/firmware/gen_bootloader.rs index 1e7ff9699174..16ef2c79a6b1 100644 --- a/drivers/gpu/nova-core/firmware/gen_bootloader.rs +++ b/drivers/gpu/nova-core/firmware/gen_bootloader.rs @@ -7,6 +7,10 @@ use kernel::{ device, + num::{ + Bounded, + TryIntoBounded, // + }, prelude::*, ptr::Alignable, sizes, // @@ -30,7 +34,7 @@ pub(crate) struct GenericBootloader { /// Bootloader code, zero-padded to a whole number of falcon memory blocks. ucode: KVec, /// Byte offset in IMEM at which the code is loaded. - imem_dst_start: u16, + imem_dst_start: Bounded, /// Tag under which the first code block is loaded. start_tag: u16, } @@ -76,7 +80,7 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result { Ok(Self { ucode, - imem_dst_start: u16::try_from(imem_dst_start)?, + imem_dst_start: imem_dst_start.try_into_bounded().ok_or(EINVAL)?, start_tag: u16::try_from(tlv.get_u32(b"STRT")?)?, }) } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index df2eddc58efb..bf3a43f1c09e 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -236,7 +236,7 @@ pub(crate) fn usable_fb_size(self) -> u64 { /// Auto-increment on write. 24:24 aincw => bool; /// IMEM block and word offset. - 15:0 offs; + 23:0 offs; } /// IMEM data register. Reading/writing this register accesses IMEM at the address -- 2.56.0