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Tue, 10 Nov 2026 04:39:17 -0800 (PST) Received: from [192.168.0.15] ([2a02:a312:c59b:a180:251a:f25f:80fa:af1d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-498363e0019sm5050033f8f.38.2026.11.10.04.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 04:39:17 -0800 (PST) From: Artur Kowalski Date: Tue, 10 Nov 2026 13:39:06 +0100 Subject: [PATCH 1/6] clocksource/drivers/timer-tegra: Keep Tegra20's watchdog timers free X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261110-t20-for-upstream-v1-1-5923449951fe@gmail.com> References: <20261110-t20-for-upstream-v1-0-5923449951fe@gmail.com> In-Reply-To: <20261110-t20-for-upstream-v1-0-5923449951fe@gmail.com> To: Daniel Lezcano , Thomas Gleixner , Thierry Reding , Jonathan Hunter , Wim Van Sebroeck , Guenter Roeck , Jonathan Corbet , Shuah Khan , Randy Dunlap , Philipp Zabel Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, clamor95@gmail.com, Artur Kowalski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5044; i=arturkow2000@gmail.com; s=default; h=from:subject:message-id; bh=Etu/NoLu3WruVoZPzD/Ywq8Sk7DCe6Ijb/ULtQBJ5v4=; b=owGbwMvMwCVmYeTc/TaVxZzxtFoSQ9ZngcL7L79FeBWs8feY9O+8qJKg34L9Pos/JxWY3d5rk rHuhPbXjlIWBjEuBlkxRRazh0JfeOZ5vd/wcmsnzBxWJpAhDFycAjCRuycYGf7MW5tvwzmnUvJy ite/gzsNdm2+LrVIhpffddvHI3O+HJ7JyDDz5tGoxFPuQR8XXmL1nf7HM4OPYZtZUb5BfHTgs71 8FzgB X-Developer-Key: i=arturkow2000@gmail.com; a=openpgp; fpr=F60710C8D69E03A01A2801CD87A47D20C2709637 Tegra20 has no watchdog block. Instead, the clock and reset controller resets the system when the interrupt of TIMER1 or TIMER2 fires while the previous one is still pending. A bootloader can start this watchdog and leave it running for the kernel. Since commit f6d50ec5f85c ("clocksource/drivers/tegra: Support per-CPU timers on all Tegra's"), the driver uses TIMER1-2 as the per-CPU clock event devices on Tegra20, where it used TIMER3 before. When CPU0's clock event device takes over TIMER1, the clock and reset controller still resets the system if a timer interrupt fires while the previous one hasn't been handled yet, which resets about half of the boots early. If the system survives that, the watchdog stays enabled but never fires, as CPU0 keeps clearing the timer's interrupts. Use TIMER3-4 for the per-CPU clock event devices on Tegra20, leaving TIMER1-2 to the watchdog. Tegra30 needs TIMER1-4 for its four CPUs and its watchdog uses TIMER5, so keep its mapping. A watchdog left running by the bootloader is then no longer disarmed, so it resets the system unless it is pinged. That needs the tegra_wdt driver, which gains Tegra20 support in the following patches, built in or loaded before the watchdog's timeout expires. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Artur Kowalski --- drivers/clocksource/timer-tegra.c | 40 ++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 35b6ce9deffa..0f63bf8bd706 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -208,10 +208,15 @@ static struct clocksource suspend_rtc_clocksource = { .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) +/* + * The timer used by a CPU is TIMER1-4 on Tegra20 and Tegra30, starting from + * @first, or TIMER10-13 on later SoCs. + */ +static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20, + unsigned int first) { if (tegra20) { - switch (cpu) { + switch (cpu + first) { case 0: return TIMER1_BASE; case 1: @@ -226,10 +231,11 @@ static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) return TIMER10_BASE + cpu * 8; } -static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) +static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20, + unsigned int first) { if (tegra20) - return TIMER1_IRQ_IDX + cpu; + return TIMER1_IRQ_IDX + first + cpu; return TIMER10_IRQ_IDX + cpu; } @@ -248,7 +254,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to, } static int __init tegra_init_timer(struct device_node *np, bool tegra20, - int rating) + int rating, unsigned int first) { struct timer_of *to; int cpu, ret; @@ -297,12 +303,18 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + if (tegra20 && first + num_possible_cpus() > 4) { + pr_err("not enough timers for %u CPUs\n", num_possible_cpus()); + ret = -EINVAL; + goto out; + } + for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING; unsigned long rate = tegra_rate_for_timer(to, tegra20); - unsigned int base = tegra_base_for_cpu(cpu, tegra20); - unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); + unsigned int base = tegra_base_for_cpu(cpu, tegra20, first); + unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20, first); unsigned int irq = irq_of_parse_and_map(np, idx); if (!irq) { @@ -376,12 +388,13 @@ static int __init tegra210_init_timer(struct device_node *np) * after CPUPORESET signal due to a system design shortcoming, * hence tegra-timer is more preferable on Tegra210. */ - return tegra_init_timer(np, false, 460); + return tegra_init_timer(np, false, 460, 0); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); static int __init tegra20_init_timer(struct device_node *np) { + unsigned int first = 0; int rating; /* @@ -398,7 +411,16 @@ static int __init tegra20_init_timer(struct device_node *np) else rating = 330; - return tegra_init_timer(np, true, rating); + /* + * Tegra20 has no watchdog block. Its watchdog is driven by TIMER1 or + * TIMER2, which the bootloader may leave running, so leave both to it + * and use TIMER3-4 for the two CPUs. Tegra30's watchdogs use TIMER5 + * and later, and its four CPUs need TIMER1-4. + */ + if (of_machine_is_compatible("nvidia,tegra20")) + first = 2; + + return tegra_init_timer(np, true, rating, first); } TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -- 2.56.0