From: Mario Limonciello <mario.limonciello@amd.com>
To: "Bjorn Helgaas" <helgaas@kernel.org>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>
Cc: Oz Tiram <oz@shift-computing.de>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <amd-gfx@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>,
Mario Limonciello <mario.limonciello@amd.com>
Subject: [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number
Date: Tue, 10 Nov 2026 16:48:21 -0600 [thread overview]
Message-ID: <20261110-vfct-regression-v5-1-f49fae981bf3@amd.com> (raw)
In-Reply-To: <20261110-vfct-regression-v5-0-f49fae981bf3@amd.com>
Bridge scans are split into two passes when bus numbers need reassigning.
Save the firmware secondary bus number on the bridge pci_dev during pass 0,
before the bridge is disabled, and keep it for pass 1 so devices discovered
there can read the original bus number via their upstream bridge.
Guard the cached value with a validity flag so later rescans do not overwrite
it with the renumbered runtime value.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pci/probe.c | 4 ++++
include/linux/pci.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 27008e2ea5afc..14b3dd7dac271 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1418,6 +1418,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
secondary, subordinate, pass);
+ if (!pass && !dev->fw_sec_busnr_valid) {
+ dev->fw_sec_busnr = secondary;
+ dev->fw_sec_busnr_valid = true;
+ }
if (!primary && (primary != bus->number) && secondary && subordinate) {
pci_warn(dev, "Primary bus is hard wired to 0\n");
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5ffcf5ce8c966..b942dbb4edf57 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -363,6 +363,8 @@ struct pci_dev {
struct pci_slot *slot; /* Physical slot this device is in */
unsigned int devfn; /* Encoded device & function index */
+ /* Firmware secondary bus number saved across bridge scan passes */
+ unsigned char fw_sec_busnr;
unsigned short vendor;
unsigned short device;
unsigned short subsystem_vendor;
@@ -414,6 +416,7 @@ struct pci_dev {
unsigned int pme_poll:1; /* Poll device's PME status bit */
unsigned int pinned:1; /* Whether this dev is pinned */
unsigned int config_rrs_sv:1; /* Config RRS software visibility */
+ unsigned int fw_sec_busnr_valid:1;
unsigned int imm_ready:1; /* Supports Immediate Readiness */
unsigned int d1_support:1; /* Low power state D1 is supported */
unsigned int d2_support:1; /* Low power state D2 is supported */
--
2.43.0
next prev parent reply other threads:[~2026-11-10 22:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 22:48 [PATCH v5 0/3] Fix amdgpu detection of pci=realloc Mario Limonciello
2026-11-10 22:48 ` Mario Limonciello [this message]
2026-11-10 22:48 ` [PATCH v5 2/3] drm/amdgpu: Match VFCT using initial PCI bus number Mario Limonciello
2026-11-10 22:48 ` [PATCH v5 3/3] drm/radeon: " Mario Limonciello
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