From: Arun Iyengar via B4 Relay <devnull+aiyengar1990.gmail.com@kernel.org>
To: "Sandy Huang" <hjc@rock-chips.com>,
"Heiko Stübner" <heiko@sntech.de>, "Andy Yan" <andyshrk@163.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Sascha Hauer" <s.hauer@pengutronix.de>
Cc: dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 3/8] drm/rockchip: vop2: Don't accept AFBC YTR for RGB565 on RK3588
Date: Tue, 10 Nov 2026 07:18:51 +0000 [thread overview]
Message-ID: <20261110-vop2-fixes-v1-3-d336e9dd90d3@gmail.com> (raw)
In-Reply-To: <20261110-vop2-fixes-v1-0-d336e9dd90d3@gmail.com>
From: Arun Iyengar <aiyengar1990@gmail.com>
The Cluster windows of the RK3588 VOP2 advertise every AFBC modifier
of format_modifiers_afbc for RGB565 and BGR565, including the ones
with the lossless colour transform (YTR). Scanning out an RGB565
buffer rendered by the Mali-G610 (panfrost) with
AFBC(16x16 | SPARSE | YTR) gives a black picture and POST_BUF_EMPTY
on the video port, on every Cluster window, while the same buffer
rendered with AFBC(16x16 | SPARSE) displays correctly, as do 32 bpp
formats with YTR.
YTR on RGB565 is also a questionable pairing to start with:
Documentation/gpu/afbc.rst requires the R, G, B component order when
YTR is used, with component 0 in the least significant bits, which
DRM_FORMAT_RGB565 (B in the low bits) doesn't have, and the Arm
Mali-D71 (komeda) only accepts AFBC for BGR565.
Stop advertising and accepting YTR for the two 16 bpp RGB formats on
RK3588, so that userspace picks a modifier the decoder handles. The
BGR565 case could not be tested (Mesa can't import BGR565 dma-bufs),
it's rejected as well because the decoder is configured identically
for both formats, apart from the R/B swap after decoding.
Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 76d151b8bc52..629ea7f11250 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -404,6 +404,18 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
if (vop2_convert_afbc_format(format) == VOP2_AFBC_FMT_INVALID)
return false;
+ /*
+ * The AFBC decoder of the RK3588 Cluster windows can't decode 16 bpp
+ * RGB that uses the lossless colour transform: the picture stays
+ * black and the video port reports POST_BUF_EMPTY, while the same
+ * buffers without YTR display fine.
+ */
+ if (vop2->version == VOP_VERSION_RK3588 && (modifier & AFBC_FORMAT_MOD_YTR) &&
+ (format == DRM_FORMAT_RGB565 || format == DRM_FORMAT_BGR565)) {
+ drm_dbg_kms(vop2->drm, "No AFBC YTR support for 16 bpp RGB\n");
+ return false;
+ }
+
/* Different windows have different format/modifier support */
for (i = 0; i < plane->modifier_count; i++) {
if (plane->modifiers[i] == modifier)
--
2.55.0
next prev parent reply other threads:[~2026-11-10 7:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 7:18 [PATCH 0/8] drm/rockchip: vop2: RK3588 clocking, sync polarity, AXI port and window fixes Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 1/8] drm/rockchip: vop2: Don't use uninitialised dividers on RK3588 Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 2/8] drm/rockchip: vop2: Fix the HDMI sync polarity " Arun Iyengar via B4 Relay
2026-11-10 7:18 ` Arun Iyengar via B4 Relay [this message]
2026-11-10 7:18 ` [PATCH 4/8] drm/rockchip: vop2: Balance window fetches across both AXI ports " Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 5/8] drm/rockchip: vop2: Report POST_BUF_EMPTY at most once per frame Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 6/8] drm/rockchip: vop2: Find the first mixer of a video port with Esmart3 too Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 7/8] drm/rockchip: vop2: Keep the other LUT_PORT_SEL fields on gamma LUT updates Arun Iyengar via B4 Relay
2026-11-10 7:18 ` [PATCH 8/8] drm/rockchip: vop2: Fix the AFBC offsets of a source that starts inside a superblock Arun Iyengar via B4 Relay
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