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charset="utf-8" Message-Id: <20261110-vop2-fixes-v1-7-d336e9dd90d3@gmail.com> References: <20261110-vop2-fixes-v1-0-d336e9dd90d3@gmail.com> In-Reply-To: <20261110-vop2-fixes-v1-0-d336e9dd90d3@gmail.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sascha Hauer Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794295129; l=1358; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=/+0LMBwuZNZCecG+Fu7CU68hi7oF5xZmzzhq/ceRbpE=; b=Fdfc8Pef3L3/LJG/JYhZ8bVLGge3v3zhLIa/A7NLxZww4zOUUh0lqK0533jFx9all8T4yvLz7 qoNNcyGyEa7Cunqff53gUq65Zr1YK7O9iVo1iwKArccs+wmYyf1Baeg X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Reply-To: aiyengar1990@gmail.com Content-Transfer-Encoding: 7bit From: Arun Iyengar On RK3588 the gamma LUT of a video port is written through a window that GAMMA_AHB_WRITE_SEL in SYS_CTRL_LUT_PORT_SEL selects. The register also holds the dclk source selection of video ports 0 and 2 and the enable of the video port 0/1 merge for modes wider than 4096 pixels, which writing the whole register clears. Only update the write select field. Signed-off-by: Arun Iyengar --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 3323e50224c5..9ad138457204 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1774,8 +1774,9 @@ static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2, struct vop2_video_port *vp, struct drm_crtc *crtc) { - vop2_writel(vop2, RK3568_LUT_PORT_SEL, - FIELD_PREP(RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, vp->id)); + regmap_update_bits(vop2->map, RK3568_LUT_PORT_SEL, + RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, + FIELD_PREP(RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, vp->id)); vop2_vp_dsp_lut_enable(vp); vop2_crtc_write_gamma_lut(vop2, crtc); vop2_vp_dsp_lut_update_enable(vp); -- 2.55.0