From: Christian Marangi <ansuelsmth@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Felix Fietkau <nbd@nbd.name>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Christian Marangi <ansuelsmth@gmail.com>
Subject: [PATCH v12 3/5] clk: en7523: protect concurrent access to reset and PCI register
Date: Tue, 10 Nov 2026 01:07:48 +0100 [thread overview]
Message-ID: <20261110000753.508-4-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20261110000753.508-1-ansuelsmth@gmail.com>
Use spinlock for concurrent access to reset and PCI register to catch case
when clock is enabled/disabled while a reset is also operated at the same
time.
Some minor rework was needed for PCI unprepare case to permit calling it
before clk_hw_register and reference the global spinlock.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 101 ++++++++++++++++++++++++++++++++++++---
1 file changed, 95 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 2baec734df9f..fbe10e4c3693 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -150,6 +150,7 @@ struct en_clk_soc_data {
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev,
struct clk_hw_onecell_data *clk_data);
+ void (*pci_unprepare)(struct device *dev, struct en_clk_gate *cg);
};
static const u32 gsw_base[] = { 400000000, 500000000 };
@@ -577,58 +578,112 @@ static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val)
static int en7523_pci_is_enabled(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
+ struct en_clk_priv *priv;
+ unsigned long flags;
+ u32 val;
+
+ priv = dev_get_drvdata(dev);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(cg->base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
- return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
+ return !!(val & REG_PCI_CONTROL_REFCLK_EN1);
}
static int en7523_pci_prepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
+
/* Need to pull device low before reset */
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
/* Enable PCIe port 1 */
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_PCI_CONTROL);
val |= REG_PCI_CONTROL_REFCLK_EN1;
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
/* Reset to default */
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_RESET_CONTROL1);
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_RESET_CONTROL1);
writel(val | mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
msleep(100);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_RESET_CONTROL1);
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(5000, 10000);
/* Release device */
- mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
+ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_PCI_CONTROL);
writel(val | mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
msleep(250);
return 0;
}
-static void en7523_pci_unprepare(struct clk_hw *hw)
+static void __en7523_pci_unprepare(struct device *dev, struct en_clk_gate *cg)
{
- struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct en_clk_priv *priv = dev_get_drvdata(dev);
void __iomem *np_base = cg->base;
+ unsigned long flags;
u32 val;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
val &= ~REG_PCI_CONTROL_REFCLK_EN1;
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void en7523_pci_unprepare(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
+
+ __en7523_pci_unprepare(dev, cg);
}
static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
@@ -648,8 +703,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
cg->base = np_base;
cg->hw.init = &init;
- if (init.ops->unprepare)
- init.ops->unprepare(&cg->hw);
+ if (soc_data->pci_unprepare)
+ soc_data->pci_unprepare(dev, cg);
if (devm_clk_hw_register(dev, &cg->hw))
return NULL;
@@ -660,22 +715,37 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
static int en7581_pci_is_enabled(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(cg->base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
return (val & mask) == mask;
}
static int en7581_pci_enable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
writel(val | mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
@@ -683,12 +753,20 @@ static int en7581_pci_enable(struct clk_hw *hw)
static void en7581_pci_disable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
}
@@ -788,21 +866,25 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
+ struct en_clk_priv *priv = dev_get_drvdata(rcdev->dev);
u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK];
void __iomem *addr = rst_data->base + offset;
bool inverted = false;
+ unsigned long flags;
u32 val;
/* For PCIC reset logic is inverted, 0:assert 1:deassert */
if (offset == REG_NP_SCU_PCIC)
inverted = true;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(addr);
if (assert ^ inverted)
val |= BIT(id % RST_NR_PER_BANK);
else
val &= ~BIT(id % RST_NR_PER_BANK);
writel(val, addr);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
@@ -823,16 +905,21 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
+ struct en_clk_priv *priv = dev_get_drvdata(rcdev->dev);
u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK];
void __iomem *addr = rst_data->base + offset;
bool inverted = false;
+ unsigned long flags;
u32 val;
/* For PCIC reset logic is inverted, 0:assert 1:deassert */
if (offset == REG_NP_SCU_PCIC)
inverted = true;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(addr) & BIT(id % RST_NR_PER_BANK);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
return inverted ? !val : !!val;
}
@@ -1223,6 +1310,7 @@ static const struct en_clk_soc_data en7523_data = {
.unprepare = en7523_pci_unprepare,
},
.hw_init = en7523_clk_hw_init,
+ .pci_unprepare = __en7523_pci_unprepare,
};
static const struct en_clk_soc_data en7581_data = {
@@ -1244,6 +1332,7 @@ static const struct en_clk_soc_data en751221_data = {
.unprepare = en7523_pci_unprepare,
},
.hw_init = en751221_clk_hw_init,
+ .pci_unprepare = __en7523_pci_unprepare,
};
static const struct of_device_id of_match_clk_en7523[] = {
--
2.55.0
next prev parent reply other threads:[~2026-11-10 0:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 0:07 [PATCH v12 0/5] clk: add support for Airoha AN7583 clock Christian Marangi
2026-11-10 0:07 ` [PATCH v12 1/5] dt-bindings: clock: airoha: Document support for " Christian Marangi
2026-11-10 0:07 ` [PATCH v12 2/5] clk: en7523: use devm variant for clk_hw_register and fixed clock Christian Marangi
2026-11-10 0:07 ` Christian Marangi [this message]
2026-11-10 0:07 ` [PATCH v12 4/5] clk: en7523: generalize register clocks function Christian Marangi
2026-11-10 0:07 ` [PATCH v12 5/5] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261110000753.508-4-ansuelsmth@gmail.com \
--to=ansuelsmth@gmail.com \
--cc=bmasney+clk@redhat.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jbrunet+clk@baylibre.com \
--cc=krzk+dt@kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=nbd@nbd.name \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®