[PATCH] drm/amdgpu: fix kernel-doc in amdgpu_gfx.h

[Ayush <ayush37735@gmail.com>]

Fix kernel-doc warnings in drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h by
adding the missing 'struct' keyword to amdgpu_rb_config, properly
formatting and aligning member documentation comments, and adding
an explicit Return: block for amdgpu_gfx_create_bitmask().

Validated with ./scripts/kernel-doc -v -none -Wall -Werror.

Signed-off-by: Ayush <ayush37735@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 31 +++++++++++--------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 5939e1fb3..96f4e4ce2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -181,7 +181,7 @@ struct amdgpu_kiq {
 #define AMDGPU_GFX_MAX_SH_PER_SE 2
 
 /**
- * amdgpu_rb_config - Configure a single Render Backend (RB)
+ * struct amdgpu_rb_config - Configure a single Render Backend (RB)
  *
  * Bad RBs are fused off and there is a harvest register the driver reads to
  * determine which RB(s) are fused off so that the driver can configure the
@@ -191,34 +191,28 @@ struct amdgpu_kiq {
  */
 struct amdgpu_rb_config {
 	/**
-	 * @rb_backend_disable:
-	 *
-	 * The value captured from register RB_BACKEND_DISABLE indicates if the
-	 * RB backend is disabled or not.
+	 * @rb_backend_disable: The value captured from register
+	 * RB_BACKEND_DISABLE indicates if the RB backend is disabled or not.
 	 */
 	uint32_t rb_backend_disable;
 
 	/**
-	 * @user_rb_backend_disable:
-	 *
-	 * The value captured from register USER_RB_BACKEND_DISABLE indicates
-	 * if the User RB backend is disabled or not.
+	 * @user_rb_backend_disable: The value captured from register
+	 * USER_RB_BACKEND_DISABLE indicates if the User RB backend is disabled
+	 * or not.
 	 */
 	uint32_t user_rb_backend_disable;
 
 	/**
-	 * @raster_config:
-	 *
-	 * To set up all of the states, it is necessary to have two registers
-	 * to keep all of the states. This field holds the first register.
+	 * @raster_config: To set up all of the states, it is necessary to have
+	 * two registers to keep all of the states. This field holds the first
+	 * register.
 	 */
 	uint32_t raster_config;
 
 	/**
-	 * @raster_config_1:
-	 *
-	 * To set up all of the states, it is necessary to have two registers
-	 * to keep all of the states. This field holds the second register.
+	 * @raster_config_1: This field holds the second register for setting
+	 * up the raster states.
 	 */
 	uint32_t raster_config_1;
 };
@@ -587,7 +581,8 @@ struct amdgpu_gfx_ras_mem_id_entry {
  * @bit_width: length of the mask
  *
  * create a variable length bit mask.
- * Returns the bitmask.
+ *
+ * Return: The generated bitmask.
  */
 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 {
-- 
2.53.0