From: Rosen Penev <rosenp@gmail.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Alban Bedel <albeu@free.fr>,
Antony Pavlov <antonynpavlov@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v2 3/6] dt-bindings: clock: ath79: add the UART1 clock
Date: Mon, 9 Nov 2026 17:36:43 -0800 [thread overview]
Message-ID: <20261110013646.1582970-4-rosenp@gmail.com> (raw)
In-Reply-To: <20261110013646.1582970-1-rosenp@gmail.com>
AR934x has a second, high speed UART that is compatible with the
qca,ar9330-uart one and can run from a 100 MHz clock instead of the
reference clock. Add an ID for its clock.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
include/dt-bindings/clock/ath79-clk.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
index eec8f399b9e6..f8a98e4d206d 100644
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -11,7 +11,8 @@
#define ATH79_CLK_AHB 2
#define ATH79_CLK_REF 3
#define ATH79_CLK_MDIO 4
+#define ATH79_CLK_UART1 5
-#define ATH79_CLK_END 5
+#define ATH79_CLK_END 6
#endif /* __DT_BINDINGS_ATH79_CLK_H */
--
2.56.0
next prev parent reply other threads:[~2026-11-10 1:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 1:36 [PATCH v2 0/6] clk: add a driver for the ath79 PLL controller Rosen Penev
2026-11-10 1:36 ` [PATCH v2 1/6] MIPS: ath79: apply the QCA956x timer workaround in setup Rosen Penev
2026-11-10 1:36 ` [PATCH v2 2/6] MIPS: ath79: move the bootstrap reference clock to setup Rosen Penev
2026-11-10 1:36 ` Rosen Penev [this message]
2026-11-10 1:36 ` [PATCH v2 4/6] dt-bindings: clock: ath79: add the PCIe PLL clock Rosen Penev
2026-11-10 1:36 ` [PATCH v2 5/6] clk: add a driver for the Atheros/Qualcomm ath79 PLL controller Rosen Penev
2026-11-10 1:36 ` [PATCH v2 6/6] MIPS: ath79: remove the old clock code Rosen Penev
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