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Mon, 09 Nov 2026 19:57:57 -0800 (PST) Received: from localhost ([164.52.124.84]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdd8d7b37casm322833a12.22.2026.11.09.19.57.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Nov 2026 19:57:56 -0800 (PST) From: Jiabin Deng To: netdev@vger.kernel.org Cc: Dragos Tatulea , Saeed Mahameed , Tariq Toukan , Mark Bloch , Leon Romanovsky , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v3] net/mlx5e: SHAMPO, Disable end padding when relaxed ordering is supported Date: Tue, 10 Nov 2026 11:57:23 +0800 Message-ID: <20261110035723.26587-1-dengjiabin2023@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When SHAMPO and relaxed ordering writes are enabled, aligned RQ end padding can corrupt received TCP data. Due to reordering, alignment padding written at the end of one packet can overwrite data from the next packet. The current RQ end padding selection avoids alignment padding for LRO, but not for SHAMPO. Extend the condition to SHAMPO to prevent this corruption. The issue was observed in a two-host test using a BlueField-3 NIC and an NVIDIA H20 GPU. In the original test with MTU 1500, 354 of 400 transfers contained corrupted data before the fix. After applying this change, all 400 transfers across eight message sizes from 32 KiB to 4 MiB, with 50 transfers per size, completed successfully, with no incorrect bytes or corrupted intervals. Fixes: e5ca8fb08ab2 ("net/mlx5e: Add control path for SHAMPO feature") Closes: https://lore.kernel.org/r/CAFxp=AY2cVRQrZvB9WNnigbsobuw11NMG-cagHx0_V+ur2ToFw@mail.gmail.com Link: https://lore.kernel.org/r/atZKOtjrb9HKSNHF@dtatulea-c5.nvidia.com Suggested-by: Dragos Tatulea Reviewed-by: Dragos Tatulea Reviewed-by: Tariq Toukan Cc: stable@vger.kernel.org Signed-off-by: Jiabin Deng --- Notes (shampo-submission): Changes in v3: - Use lore.kernel.org links for the original report and fix discussion. - Add Tariq Toukan's Reviewed-by tag. - Cc the netdev maintainers and linux-rdma mailing list. - No code changes. v2: https://lore.kernel.org/netdev/20261109034444.11241-1-dengjiabin2023@gmail.com/ Changes in v2: - Clarify that the corruption is not specific to GPU or DMA-BUF memory. - Explain how reordered alignment padding can overwrite the next packet's data. - Add Dragos Tatulea's Reviewed-by tag. - No code changes. v1: https://lore.kernel.org/netdev/20261106083719.22798-1-dengjiabin2023@gmail.com/ drivers/net/ethernet/mellanox/mlx5/core/en/params.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index 5caf7820a136..159f79302a08 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -911,10 +911,11 @@ static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) { - bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO; + bool no_pad = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO || + params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO; bool ro = MLX5_CAP_GEN(mdev, relaxed_ordering_write); - return ro && lro_en ? + return ro && no_pad ? MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; } base-commit: fafbc4051123d5459ea6950899cec08ed946e278 -- 2.51.0