From: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
To: "Jonathan Cameron" <jic23@kernel.org>,
"David Lechner" <dlechner@baylibre.com>,
"Nuno Sá" <nuno.sa@analog.com>,
"Andy Shevchenko" <andy@kernel.org>,
"Michal Simek" <michal.simek@amd.com>,
"Conall O'Griofa" <conall.ogriofa@amd.com>
Cc: <linux-iio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <git@amd.com>,
Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>,
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Subject: [PATCH v5 05/16] iio: adc: xilinx-xadc: Use bitfield helpers and bit macros
Date: Tue, 10 Nov 2026 10:31:50 +0530 [thread overview]
Message-ID: <20261110050201.1850399-6-dileepkumar.nagavarapu@amd.com> (raw)
In-Reply-To: <20261110050201.1850399-1-dileepkumar.nagavarapu@amd.com>
Replace open-coded bit manipulation with FIELD_GET(),
FIELD_PREP(), BIT(), and GENMASK() helpers.
Using the kernel bitfield helpers improves readability and
makes bit operations less error-prone.
No functional changes intended.
Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
---
drivers/iio/adc/xilinx-xadc-core.c | 50 ++++++++++++++++++------------
drivers/iio/adc/xilinx-xadc.h | 29 +++++++++--------
2 files changed, 46 insertions(+), 33 deletions(-)
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index 66c6f3319ca0..eb63675464bb 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -11,6 +11,8 @@
* - AXI XADC interface: Xilinx PG019
*/
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
@@ -47,28 +49,28 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
#define XADC_ZYNQ_REG_CTL 0x18
#define XADC_ZYNQ_CFG_ENABLE BIT(31)
-#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
+#define XADC_ZYNQ_CFG_CFIFOTH_MASK GENMASK(23, 20)
#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
-#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
+#define XADC_ZYNQ_CFG_DFIFOTH_MASK GENMASK(19, 16)
#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
#define XADC_ZYNQ_CFG_WEDGE BIT(13)
#define XADC_ZYNQ_CFG_REDGE BIT(12)
-#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
-#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
+#define XADC_ZYNQ_CFG_TCKRATE_MASK GENMASK(9, 8)
+#define XADC_ZYNQ_CFG_TCKRATE_DIV2 0
+#define XADC_ZYNQ_CFG_TCKRATE_DIV4 1
+#define XADC_ZYNQ_CFG_TCKRATE_DIV8 2
+#define XADC_ZYNQ_CFG_TCKRATE_DIV16 3
+#define XADC_ZYNQ_CFG_IGAP_MASK GENMASK(4, 0)
#define XADC_ZYNQ_CFG_IGAP(x) (x)
#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
-#define XADC_ZYNQ_INT_ALARM_MASK 0xff
+#define XADC_ZYNQ_INT_ALARM_MASK GENMASK(7, 0)
#define XADC_ZYNQ_INT_ALARM_OFFSET 0
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
+#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK GENMASK(19, 16)
#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
+#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK GENMASK(15, 12)
#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
#define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
#define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
@@ -105,7 +107,12 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
#define XADC_AXI_GIER_ENABLE BIT(31)
#define XADC_AXI_INT_EOS BIT(4)
-#define XADC_AXI_INT_ALARM_MASK 0x3c0f
+#define XADC_AXI_INT_ALARM_OT BIT(0)
+#define XADC_AXI_INT_ALARM_TEMP_SUPPLY GENMASK(3, 1)
+#define XADC_AXI_INT_ALARM_SUPPLY GENMASK(13, 10)
+#define XADC_AXI_INT_ALARM_MASK (XADC_AXI_INT_ALARM_SUPPLY | \
+ XADC_AXI_INT_ALARM_TEMP_SUPPLY | \
+ XADC_AXI_INT_ALARM_OT)
#define XADC_FLAGS_BUFFERED BIT(0)
#define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
@@ -215,7 +222,7 @@ static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
- tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
+ tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
@@ -373,7 +380,8 @@ static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_d
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
- XADC_ZYNQ_CFG_REDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
+ XADC_ZYNQ_CFG_REDGE | FIELD_PREP(XADC_ZYNQ_CFG_TCKRATE_MASK, tck_div) |
+ XADC_ZYNQ_CFG_IGAP(igap));
if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
ret = clk_set_rate(xadc->clk, pcap_rate);
@@ -391,7 +399,7 @@ static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
- switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
+ switch (FIELD_GET(XADC_ZYNQ_CFG_TCKRATE_MASK, val)) {
case XADC_ZYNQ_CFG_TCKRATE_DIV4:
div = 4;
break;
@@ -760,7 +768,8 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
break;
}
- return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, val);
+ return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
+ FIELD_PREP(XADC_CONF2_PD_MASK, val));
}
static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
@@ -807,7 +816,8 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
if (ret)
return ret;
- ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
+ ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
+ FIELD_PREP(XADC_CONF1_SEQ_MASK, seq_mode));
if (ret)
return ret;
@@ -822,7 +832,7 @@ static int xadc_preenable(struct iio_dev *indio_dev)
int ret;
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
- XADC_CONF1_SEQ_DEFAULT);
+ FIELD_PREP(XADC_CONF1_SEQ_MASK, XADC_CONF1_SEQ_DEFAULT));
if (ret)
goto err;
@@ -876,7 +886,7 @@ static int xadc_read_samplerate(struct xadc *xadc)
if (ret)
return ret;
- div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
+ div = FIELD_GET(XADC_CONF2_DIV_MASK, val16);
if (div < 2)
div = 2;
@@ -984,7 +994,7 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
div = 0xff;
return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
- div << XADC_CONF2_DIV_OFFSET);
+ FIELD_PREP(XADC_CONF2_DIV_MASK, div));
}
static int xadc_write_raw(struct iio_dev *indio_dev,
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index fb911ed87600..f5bf2d08eedc 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -9,6 +9,7 @@
#ifndef __IIO_XILINX_XADC__
#define __IIO_XILINX_XADC__
+#include <linux/bits.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
@@ -159,22 +160,24 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
#define XADC_CONF0_MUX BIT(11)
#define XADC_CONF0_CHAN(x) (x)
-#define XADC_CONF1_SEQ_MASK (0xf << 12)
-#define XADC_CONF1_SEQ_DEFAULT (0 << 12)
-#define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12)
-#define XADC_CONF1_SEQ_CONTINUOUS (2 << 12)
-#define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12)
-#define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
-#define XADC_CONF1_SEQ_INDEPENDENT (8 << 12)
-#define XADC_CONF1_ALARM_MASK 0x0f0f
+#define XADC_CONF1_SEQ_MASK GENMASK(15, 12)
+#define XADC_CONF1_SEQ_DEFAULT 0
+#define XADC_CONF1_SEQ_SINGLE_PASS 1
+#define XADC_CONF1_SEQ_CONTINUOUS 2
+#define XADC_CONF1_SEQ_SINGLE_CHANNEL 3
+#define XADC_CONF1_SEQ_SIMULTANEOUS 4
+#define XADC_CONF1_SEQ_INDEPENDENT 8
+#define XADC_CONF1_ALARM_LOW_MASK GENMASK(3, 0)
+#define XADC_CONF1_ALARM_HIGH_MASK GENMASK(11, 8)
+#define XADC_CONF1_ALARM_MASK (XADC_CONF1_ALARM_HIGH_MASK | XADC_CONF1_ALARM_LOW_MASK)
-#define XADC_CONF2_DIV_MASK 0xff00
+#define XADC_CONF2_DIV_MASK GENMASK(15, 8)
#define XADC_CONF2_DIV_OFFSET 8
-#define XADC_CONF2_PD_MASK (0x3 << 4)
-#define XADC_CONF2_PD_NONE (0x0 << 4)
-#define XADC_CONF2_PD_ADC_B (0x2 << 4)
-#define XADC_CONF2_PD_BOTH (0x3 << 4)
+#define XADC_CONF2_PD_MASK GENMASK(5, 4)
+#define XADC_CONF2_PD_NONE 0
+#define XADC_CONF2_PD_ADC_B 2
+#define XADC_CONF2_PD_BOTH 3
#define XADC_ALARM_TEMP_MASK BIT(0)
#define XADC_ALARM_VCCINT_MASK BIT(1)
--
2.34.1
next prev parent reply other threads:[~2026-11-10 5:08 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 5:01 [PATCH v5 00/16] iio: adc: xilinx-xadc: Add I2C interface support for System Management Wizard Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 01/16] iio: adc: xilinx-xadc: Correct write edge in CFG Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 02/16] iio: adc: xilinx-xadc: Fix coding style issues Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 03/16] iio: adc: xilinx-xadc: Use kernel integer types Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 04/16] iio: adc: xilinx-xadc: Drop unnecessary masking and dead code Dileep Kumar Nagavarapu
2026-11-10 5:01 ` Dileep Kumar Nagavarapu [this message]
2026-11-10 5:01 ` [PATCH v5 06/16] iio: adc: xilinx-xadc: Use guard()/scoped_guard() for spinlock locking Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 07/16] iio: adc: xilinx-xadc: Use guard() for mutex locking Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 08/16] iio: adc: xilinx-xadc: Simplify common coding patterns Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 09/16] iio: adc: xilinx-xadc: Add unit suffixes to macro names Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 10/16] iio: adc: xilinx-xadc: Include appropriate header files Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 11/16] iio: adc: xilinx-xadc: Add clarifying comments Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 12/16] iio: adc: xilinx-xadc: Refine Zynq read/write error handling on timeout/interrupt Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 13/16] iio: adc: xilinx-xadc: Add helper functions for the device setup Dileep Kumar Nagavarapu
2026-11-10 5:01 ` [PATCH v5 14/16] iio: adc: xilinx-xadc: Split driver into core and platform files Dileep Kumar Nagavarapu
2026-11-10 5:02 ` [PATCH v5 15/16] iio: adc: xilinx-xadc: Add .setup_channels() to struct xadc_ops Dileep Kumar Nagavarapu
2026-11-10 5:02 ` [PATCH v5 16/16] iio: adc: xilinx-xadc: Add I2C interface support Dileep Kumar Nagavarapu
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