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(unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 542170ae8; Tue, 10 Nov 2026 15:45:39 +0800 (GMT+08:00) From: Damon Ding To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Neil Armstrong , Manivannan Sadhasivam , Luca Ceresoli , Dmitry Baryshkov , Sebastian Reichel , Dave Jones , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Damon Ding Subject: [PATCH v5 1/3] dt-bindings: phy: Add rockchip,rk3568-edp-phy Date: Tue, 10 Nov 2026 15:45:31 +0800 Message-Id: <20261110074533.4052196-2-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261110074533.4052196-1-damon.ding@rock-chips.com> References: <20261110074533.4052196-1-damon.ding@rock-chips.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Tid: 0aa1c46b771c03a8kunm3f9229952eb2d7 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkZTUtKVkpIQ09OS0JIThpOQlYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU JDQ0xVSktLVUtZBg++ DKIM-Signature: a=rsa-sha256; b=F04h+i5YOdJj+eYumMaoHEpQ/Y9uPBnFxpIVcFtHUV8q1/w6Ldkls9udjkG6jXZr/IK57dmfyuYmDnUxqm19j6NvANHvEaHou7FjAh12zj3aamx9LSu84tlB5BwlZ07jspMI+2dwQQY0hbz+jYW3yH5/CNnSbCV+rG1e+CnbB9s=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=z3zcGefP/ImEsmdAlTDnpQ/14sBuInMfCFAd504HG5Q=; h=date:mime-version:subject:message-id:from; Document the eDP transmitter PHY with Naneng IP block found on the RK3568 SoC. The PHY has its own register window inside the eDP PHY GRF, so its node is modeled as a child of the eDP PHY GRF syscon with a reg property describing that window. Also add the "rockchip,rk3568-edp-phy-grf" compatible with its own binding schema, so the shared Rockchip GRF schema is not extended with per-device conditionals. Signed-off-by: Damon Ding --- Changes in v4: - Add the reg entry for the PHY node and the ranges/#address-cells/ #size-cells for the parent syscon node. Changes in v5: - Move the APB clock (PCLK_EDPPHY_GRF) from the parent syscon node to the PHY node, matching the updated driver. - Split the "rockchip,rk3568-edp-phy-grf" syscon node to its own binding schema, instead of extending the shared Rockchip GRF schema. - Rename the reference clock to "ref". - Drop the example from the PHY binding schema, as complete MFD examples belong in the GRF binding schema. --- .../bindings/phy/rockchip,rk3568-edp-phy.yaml | 46 +++++++++++ .../rockchip/rockchip,rk3568-edp-phy-grf.yaml | 80 +++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip,rk3568-edp-phy-grf.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml new file mode 100644 index 000000000000..06dd1d19dca2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3568-edp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip eDP Transmitter PHY with Naneng IP block + +maintainers: + - Damon Ding + - Heiko Stuebner + +description: + On the RK3568 SoC the eDP PHY is controlled through the eDP PHY GRF + registers, therefore the PHY node is expected to be a child of the + eDP PHY GRF syscon node. + +properties: + compatible: + const: rockchip,rk3568-edp-phy + + reg: + maxItems: 1 + description: PHY registers within the eDP PHY GRF. + + clocks: + items: + - description: Reference clock from the PMU CRU + - description: APB clock gating the PHY register window + + clock-names: + items: + - const: ref + - const: apb + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/soc/rockchip/rockchip,rk3568-edp-phy-grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/rockchip,rk3568-edp-phy-grf.yaml new file mode 100644 index 000000000000..852420798f06 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/rockchip/rockchip,rk3568-edp-phy-grf.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/rockchip/rockchip,rk3568-edp-phy-grf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip eDP PHY GRF on the RK3568 SoC + +maintainers: + - Damon Ding + - Heiko Stuebner + +description: + The eDP PHY GRF is a dedicated register file on the RK3568 SoC, + holding the registers used by the eDP Transmitter PHY with Naneng IP + block. The PHY itself is modeled as a child node, with its reg + property describing the PHY register window inside the GRF. + +properties: + compatible: + items: + - const: rockchip,rk3568-edp-phy-grf + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + $ref: /schemas/phy/rockchip,rk3568-edp-phy.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdcb0000 0x0 0x8000>; + clocks = <&cru PCLK_EDPPHY_GRF>; + ranges = <0x0 0x0 0xfdcb0000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + edp_phy: phy@0 { + compatible = "rockchip,rk3568-edp-phy"; + reg = <0x0 0x100>; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + }; + }; + }; -- 2.34.1