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Tue, 10 Nov 2026 02:12:54 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 10 Nov 2026 02:12:50 -0800 From: Sumit Gupta To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2] cpufreq: CPPC: Set CPPC Enable register in cpu_init Date: Tue, 10 Nov 2026 15:42:46 +0530 Message-ID: <20261110101246.3665797-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF00079401:EE_|DS2PR12MB108293:EE_ X-MS-Office365-Filtering-Correlation-Id: 74185d4b-1629-4f20-316e-08df3f1338fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|7416014|23010399003|56012099006|11063799006|18002099003|10067099003|261009223027099003|261102123227099003|261026140227099003|261021123027099003|261021121427099003|261022105027099003|261028144727099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fw2V6ZyeRXumNIYwUbsbApZq2v7MJlS4n2/Q/NZh7ZgBTrqsDiDpXA1O0cvu8etncrhOno5W3vU6S6MGWe7UXWVLRjxSeUvutzHXHR5nsWFPfR5Pp7M5f+IsbXY+kQbUBrWWdaKrc/huP+nYG4vFlSQ4Ufw8fazS3+awkPrdun5YjYkubqcG+x6g+rxtCjhnDkUBUK8HJ5wqWCQ89/FqhROI9iqhbwKtnESVHsUZ2EidCeUCWn15eq2v8KGxf7Ki5XmulJo5dtIaNxDbXDSfiRJ3ZbU+MRUlfWH7e7Tk+ZGRcHdk/ywJiz9wGLpMpSV/I86kVWxdP+EGSkjMqj8zoTOgiaclUJBAcqUN6H7Bx+IbAjCnCJ60ORz4cVu8EMBK+1cyMmOO5dghzjUfpnanqrMU83rWd60SkowWtvwho7IWUP4+3yKaU6ql7oMd1m32 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 10:13:10.1047 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74185d4b-1629-4f20-316e-08df3f1338fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF00079401.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB108293 As per ACPI 6.x s8.4.6.1.4 (CPPC Enable Register): "If supported by the platform, OSPM writes a one to this register to enable CPPC on this processor. If not implemented, OSPM assumes the platform always has CPPC enabled." The driver never writes this register. CPPC therefore stays disabled on platforms such as NVIDIA GB10 that wait for OSPM to enable it. Call cppc_set_enable() in cppc_cpufreq_cpu_init(). Fail init if enabling CPPC fails. If init fails after CPPC is enabled, disable it again. The register is optional, so -EOPNOTSUPP is not an error. This relies on commit ab482f1bac6b ("ACPI: CPPC: Refactor register value get and set ABIs") from v6.16. Before it, cppc_set_enable() returned -EFAULT instead of -EOPNOTSUPP when the Enable register is not implemented. On an older kernel this change would make init fail on every platform without the register, so the stable range starts at v6.16. Fixes: 5477fb3bd1e8 ("ACPI / CPPC: Add a CPUFreq driver for use with CPPC") Cc: stable@vger.kernel.org # v6.16+ Signed-off-by: Sumit Gupta --- v1 -> v2: - Fail init if enabling CPPC fails and disable CPPC again if init fails after enabling it (Christian). - Move enable after the policy->shared_type check, so cppc_set_perf() is the only failure after it. - Mention NVIDIA GB10 in the commit message (Christian). v1: https://lore.kernel.org/lkml/20261105123244.3132560-1-sumitg@nvidia.com/ drivers/cpufreq/cppc_cpufreq.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 957fa7775260..b2af24ae5008 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -714,7 +714,17 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) pr_debug("Unsupported CPU co-ord type: %d\n", policy->shared_type); ret = -EFAULT; - goto out; + goto out_put; + } + + /* + * Enable CPPC. The Enable register is optional - some platforms + * may not support it. + */ + ret = cppc_set_enable(cpu, true); + if (ret && ret != -EOPNOTSUPP) { + pr_err("Failed to enable CPPC for CPU%u (%d)\n", cpu, ret); + goto out_put; } policy->fast_switch_possible = cppc_allow_fast_switch(policy->cpus); @@ -742,6 +752,8 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) return 0; out: + cppc_set_enable(cpu, false); +out_put: cppc_cpufreq_put_cpu_data(policy); return ret; } -- 2.34.1