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Tue, 10 Nov 2026 05:15:32 -0800 (PST) Received: from desktop.home ([46.205.207.69]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b75790353asm1126372a12.31.2026.11.10.05.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 05:15:32 -0800 (PST) From: =?UTF-8?q?Andrzej=20Pi=C4=85tyszek?= To: amd-gfx@lists.freedesktop.org Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Fangzhi Zuo , Relja Vojvodic , Ilya Bakoulin , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andrzej=20Pi=C4=85tyszek?= Subject: [PATCH 1/3] drm/amd/display: Apply requested TxFFE level right away in FRL training Date: Tue, 10 Nov 2026 14:09:54 +0100 Message-ID: <20261110130956.160024-2-andrzej.piatyszek@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261110130956.160024-1-andrzej.piatyszek@gmail.com> References: <20261110130956.160024-1-andrzej.piatyszek@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the sink answers an LTP request with 0xE (next TxFFE level) in LTS:3, hdmi_frl_perform_link_training() programs the new level only on the next poll, and only if the sink has set FLT_update again by then. The sink usually has not, as the driver has just cleared FLT_update. The sink keeps asking, and current_FFE advances without reaching the PHY. A Samsung QE65Q80T (2020) needs one TxFFE step at 10 Gbps x 4, so its link mostly ends up at 6 Gbps x 3. Program the requested level right away and drop the deferred programming. Fixes: cbb8e2044b9e ("drm/amd/display: Add DC link support for FRL") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Andrzej Piątyszek --- .../display/dc/link/protocols/link_hdmi_frl.c | 33 ++++++++----------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c index 960f18fe2..78e62bfec 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c @@ -640,26 +640,6 @@ static enum link_result hdmi_frl_perform_link_training(struct ddc_service *ddc_s prev_flt_update = scdc_update.fields.FLT_UPDATE; } - /*Set TxFFE = TxFFE0*/ - /*Program FFE_Levels - scdc_config has this field at 0 */ - if (override_FFE) { - if (current_FFE == 0) - dio_link_enc->funcs->prog_eq_setting(dio_link_enc, current_FFE, - test_req.fields.TXFFE_DEEMPHASIS, - test_req.fields.TXFFE_PRESHOOT, - test_req.fields.TXFFE_NOFFE, - link_settings); - else { - if (scdc_update.fields.FLT_UPDATE) - dio_link_enc->funcs->prog_eq_setting(dio_link_enc, current_FFE, - test_req.fields.TXFFE_DEEMPHASIS, - test_req.fields.TXFFE_PRESHOOT, - test_req.fields.TXFFE_NOFFE, - link_settings); - } - FRL_INFO("FRL LINK TRAINING: TxFFE = %d.\n", current_FFE); - override_FFE = false; - } if (scdc_update.fields.FLT_UPDATE) { offset = HDMI_SCDC_LTP_REQ; link_query_ddc_data(ddc_service, slave_address, @@ -749,6 +729,19 @@ static enum link_result hdmi_frl_perform_link_training(struct ddc_service *ddc_s ln1_pattern = pre_ln1_pattern; ln2_pattern = pre_ln2_pattern; ln3_pattern = pre_ln3_pattern; + + /* + * The sink re-evaluates the link as soon as FLT_update + * is cleared, so program the requested level now. + */ + dio_link_enc->funcs->prog_eq_setting(dio_link_enc, + current_FFE, + test_req.fields.TXFFE_DEEMPHASIS, + test_req.fields.TXFFE_PRESHOOT, + test_req.fields.TXFFE_NOFFE, + link_settings); + FRL_INFO("FRL LINK TRAINING: TxFFE = %d.\n", current_FFE); + override_FFE = false; } FRL_INFO("FRL LINK TRAINING: Setting Training Pattern [ln0,ln1,ln2,ln3] = [%d,%d,%d,%d].\n", -- 2.56.0