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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91ef04f89c1sm22998676d6.23.2026.11.10.07.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 07:18:50 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xQncX-000000063UD-2Q7t; Tue, 10 Nov 2026 11:18:49 -0400 Date: Tue, 10 Nov 2026 11:18:49 -0400 From: Jason Gunthorpe To: Mostafa Saleh Cc: xuheng@cs.columbia.edu, Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] iommu/arm-smmu-v3: Invalidate a new level-1 stream table descriptor Message-ID: <20261110151849.GZ663069@ziepe.ca> References: <20261109-smmu-l1std-cfgi-v1-1-65e5203a6516@cs.columbia.edu> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Nov 10, 2026 at 02:58:21PM +0000, Mostafa Saleh wrote: > On Mon, Nov 09, 2026 at 09:36:54PM +0000, Xuheng Li via B4 Relay wrote: > > From: Xuheng Li > > > > arm_smmu_init_l2_strtab() allocates a level-2 stream table when the first > > master in its range is added, and makes the level-1 descriptor valid. It > > issues no invalidation, and the attach that follows sends only the leaf > > form of CMD_CFGI_STE. > > > > IHI 0070 5.1.1 requires the non-leaf form of CMD_CFGI_STE when an L1STD > > changes, including when an inactive descriptor with Span == 0 becomes > > active. An SMMU that cached the inactive descriptor can keep terminating > > the master's transactions as if its StreamID were invalid. > > > > Looking at the spec it says: > An STE or L1STD that is successfully fetched might be cached by the > SMMU in any state, therefore any modification, commissioning or > decommissioning of an STE must be followed by a CMD_CFGI_STE command. I think the patch is pointing at this: * Changing an inactive L1STD with Span == 0 to a non-zero active Span (introducing a new section of level-2 Stream table) requires an invalidation of the L1STD only. As no STEs were reachable for StreamIDs within the span, none require invalidation. Which is really explicit what to do.. > Which checks out. However, I am curious why this was not seen for > over 10 years with the current behaviour as I doubt any existing > implementation will do negative caching. Is that something that was > observed or found by inspection? Honestly I don't think there is much value in negatively caching table structure. Negatively caching the resulting leaf is good enough. > > @@ -2053,6 +2054,14 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) > > ARRAY_SIZE((*l2table)->stes)); > > arm_smmu_write_strtab_l1_desc(&cfg->l2.l1tab[arm_smmu_strtab_l1_idx(sid)], > > l2ptr_dma); > > + > > + /* > > + * The SMMU may have cached the old, invalid L1 descriptor. Making it > > + * valid needs the non-leaf form of CMD_CFGI_STE (IHI 0070 5.1.1). > > + */ All the versions are 0070, you should specify rev H.a if citing the spec Reviewed-by: Jason Gunthorpe Jason