Re: [PATCH v8 0/3] usb: dwc3: two Type-C connectors sharing one HS data bus

[Rob Herring <robh@kernel.org>]

On Fri, Nov 06, 2026 at 07:42:05PM +0800, Qianhui Xu wrote:
> *** AI-assistance disclosure ***
> This cover letter and the patches below were prepared with the help of an
> LLM coding assistant.  The author reviewed every line, ran every gate
> quoted in this letter himself, and takes full responsibility for the
> content.
> 
> This is a re-post of the series sent a few minutes ago (Message-ID
> <20261106112811.963923-1-xiaqinghuan@mail.ustc.edu.cn>): that posting lost
> the version tag in the per-patch subjects -- they went out as "[PATCH 1/3]"
> while the cover said v7 -- which is a tooling slip on my side.  The patch
> content is unchanged, only the subject lines differ, so the review of that
> posting still applies.  Apologies for the noise.
> 
> This is one complete, self-contained series of three patches: the binding,
> the role-switch lookup it needs, and the DWC3 arbitration between the two
> connectors.  Nothing is to be applied on top of it, and no patch of it is
> posted separately.  It supersedes the v4 series
> (<20261026123211.243224-1-xiaqinghuan@mail.ustc.edu.cn>), the v5 fixups
> (<20261031150154.1106455-1-xiaqinghuan@mail.ustc.edu.cn>) and the 11-04
> posting (<20261104032706.210042-1-xiaqinghuan@mail.ustc.edu.cn>) in full:
> their content is folded into the three patches below.  3/3 additionally
> answers the two High findings of the review of the 11-04 posting.
> 
> Two connectors on one DWC3 controller
> =====================================
> 
> The board (Lenovo Legion Y700 4th gen, SM8750) wires the Super Speed pairs
> of two USB-C receptacles to separate PHYs, while the High Speed D+/D- pair
> is shared through a 2:1 mux controlled by a single GPIO.  Both connectors
> are data-role dual and hand their role to the SoC through pmic-glink, so
> the controller has to arbitrate between two independent role requests and
> move the shared data path before it is reinitialised.
> 
> 	usb@a600000 {
> 		port-select-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;

Use the gpio mux binding.

> 
> 		ports {
> 			port@0 {			/* HS path, connector 0 */
> 				endpoint {
> 					remote-endpoint = <&usb_0_dwc3_hs>;
> 					usb-role-switch;
> 					mux-state = <0>;
> 				};
> 			};
> 
> 			port@1 {			/* Super Speed, QMP PHY */
> 			};
> 
> 			port@2 {			/* HS path, connector 1 */
> 				endpoint {
> 					remote-endpoint = <&usb_1_dwc3_hs>;
> 					usb-role-switch;
> 					mux-state = <1>;
> 				};
> 			};

ports are for separate data streams. Endpoints are for mux'ed data 
streams. This looks like the latter, so port@0 should have 2 endpoints 
and port@2 dropped.

Rob