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[86.58.12.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4983585c4fdsm5888355f8f.10.2026.11.10.08.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 08:39:08 -0800 (PST) From: Jernej Skrabec To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , Icenowy Zheng Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH] clk: sunxi-ng: h6: Keep both parents running while switching VP9 clock Date: Tue, 10 Nov 2026 17:39:04 +0100 Message-ID: <20261110163904.1098187-1-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The VP9 clock mux only switches while both parents are running. Its reset default parent is pll-ve, which is off at boot. When the Hantro driver sets the clock rate to 300 MHz, the clock gets reparented to pll-periph0-2x, but the mux doesn't actually switch until pll-ve is enabled for the video engine. Until then, the VP9 decoder has no clock and every frame times out. Set CLK_OPS_PARENT_ENABLE, so both parents are enabled during the switch. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 7fccda96d444..a10f0502c5c1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -336,12 +336,17 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0, static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2", 0x6bc, BIT(0), 0); +/* + * The mux only switches while both parents run. pll-ve is off at boot, so + * moving the clock away from it would otherwise leave the VP9 decoder + * without a clock until pll-ve gets enabled for the video engine. + */ static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" }; static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0, 0, 3, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ - 0); + CLK_OPS_PARENT_ENABLE); static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2", 0x6cc, BIT(0), 0); -- 2.43.0