From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=46.4.11.11 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794332395; b=IkuXs//kUSDLHvsbPPBL61LPcsB+GRdaZP7jodIuX/uGhm9vuQdmns1ftgtpVVZQIrkk RxuPafq4yQhAOT9RM/hn/8wJTbLDKt2BMYoMHsltYj8Z+YUJaFgr8Yk2ohQBXduYZ7ZOZ zWa0+C1RzhemyPUP0lJXnsWJisxs/zWqi6efVTpVI+BSVEKY8dL6L/rP9WY1hK+XKvwnT JJQp2Wd4CasiBndD/n7xWBvX7JFfcYR/vkMS7lfURIylBTe5sO37/ufmnrCbWu0SkQruf gHfEbmSksUcUl7h9OPcrGIWFz6IXaIWD34PIdn7dfGjtjkw8s76YyGsnKzXEcgzLYRw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794332395; h=DMARC-Filter:Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer: In-Reply-To:References:MIME-Version:Content-Transfer-Encoding; bh=7vdZotvX6OCfjq3cA5+TdLbCY+mxRKfqeiUrbolFA94=; b=Qcczppqlr5XVgiWLdOtvBO7EySPjZHfeoy2m78MKw8CWhKaGSJZsgIqrS79LA97rE+eL B/1CUQgeXNHx7zXhhn3ZaGnff2UTqPUCJCW058Q+Yg4CDqLwAmJDAtna9rDDSiQptUuQx U51rip2wg6Zu4tZ8AGtuQ5tT/absu2e/XAjHmpMf597uDRNymnQdu4N3WMg1U4h2eRzTC wv1l6clshflRvsYeam9zBQpxT8JzTXfAOQpoJORfH9Bgs2HQLpf/t8+RrmvY/Q/Sy5e3F uGNBdY5cV7fQOfWyYzTn5qAGYoW4dUwY8ugLCNoWWDkCBHXyLz3u8xCUsgy01IkdcFQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none header.from=phrozen.org; spf=pass smtp.mailfrom=phrozen.org; arc=none smtp.remote-ip=46.4.11.11 Received: from nbd.name (nbd.name [46.4.11.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDA0F606A338; Tue, 10 Nov 2026 17:39:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org CDA0F606A338 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=phrozen.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=phrozen.org Received: from [2a04:4540:1403:9bfc:b113:5373:d0ec:2ad1] (helo=bertha10..) by ds12 with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1xQpp0-001CWh-1E; Tue, 10 Nov 2026 18:39:50 +0100 From: John Crispin To: Lorenzo Bianconi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski Cc: Ahmed Naseef , Benjamin Larsson , Christian Marangi , devicetree@vger.kernel.org, lei.dong@airoha.com, Linqi.zhang@airoha.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, mfd@lists.linux.dev, Mikhail Kshevetskiy , Rajeev.kumar@airoha.com, upstream@airoha.com, Weifeng.xu@airoha.com, zhengping.zhang@airoha.com Subject: [PATCH 6/7] pinctrl: airoha: move the GPIO register offsets to the common header Date: Tue, 10 Nov 2026 18:39:40 +0100 Message-Id: <20261110173941.301478-7-john@phrozen.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261110173941.301478-1-john@phrozen.org> References: <20261110173941.301478-1-john@phrozen.org> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The GPIO register offsets are private to pinctrl-airoha.c, which builds the shared 64 pin register table from them. A SoC with more GPIO banks needs its own table, built from the same offsets and its own for the extra banks. Move the offsets to airoha-common.h so the SoC drivers can use them. No functional change. Signed-off-by: John Crispin --- drivers/pinctrl/airoha/airoha-common.h | 20 ++++++++++++++++++++ drivers/pinctrl/airoha/pinctrl-airoha.c | 20 -------------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h index adfce89493f0..dc9b897ea77c 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -34,6 +34,26 @@ #include "../pinconf.h" #include "../pinmux.h" +/* GPIOs */ +#define REG_GPIO_CTRL 0x0000 +#define REG_GPIO_DATA 0x0004 +#define REG_GPIO_INT 0x0008 +#define REG_GPIO_INT_EDGE 0x000c +#define REG_GPIO_INT_LEVEL 0x0010 +#define REG_GPIO_OE 0x0014 +#define REG_GPIO_CTRL1 0x0020 +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 +#define REG_GPIO_DATA1 0x0070 +#define REG_GPIO_OE1 0x0078 +#define REG_GPIO_INT1 0x007c +#define REG_GPIO_INT_EDGE1 0x0080 +#define REG_GPIO_INT_EDGE2 0x0084 +#define REG_GPIO_INT_EDGE3 0x0088 +#define REG_GPIO_INT_LEVEL1 0x008c +#define REG_GPIO_INT_LEVEL2 0x0090 +#define REG_GPIO_INT_LEVEL3 0x0094 + #define AIROHA_NUM_PINS 64 #define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) #define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index a805f542bc7b..8f901f251c00 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -7,26 +7,6 @@ #include "airoha-common.h" -/* GPIOs */ -#define REG_GPIO_CTRL 0x0000 -#define REG_GPIO_DATA 0x0004 -#define REG_GPIO_INT 0x0008 -#define REG_GPIO_INT_EDGE 0x000c -#define REG_GPIO_INT_LEVEL 0x0010 -#define REG_GPIO_OE 0x0014 -#define REG_GPIO_CTRL1 0x0020 -#define REG_GPIO_CTRL2 0x0060 -#define REG_GPIO_CTRL3 0x0064 -#define REG_GPIO_DATA1 0x0070 -#define REG_GPIO_OE1 0x0078 -#define REG_GPIO_INT1 0x007c -#define REG_GPIO_INT_EDGE1 0x0080 -#define REG_GPIO_INT_EDGE2 0x0084 -#define REG_GPIO_INT_EDGE3 0x0088 -#define REG_GPIO_INT_LEVEL1 0x008c -#define REG_GPIO_INT_LEVEL2 0x0090 -#define REG_GPIO_INT_LEVEL3 0x0094 - #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ (pin), (val)) -- 2.34.1