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Tue, 10 Nov 2026 10:39:18 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 10 Nov 2026 10:39:11 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Bobby Eshleman , Carolina Jubran , Cosmin Ratiu , Daniel Borkmann , David Wei , Dragos Tatulea , Erfan Sharafzadeh , Gal Pressman , Jacob Keller , Kaifeng Wang , Leon Romanovsky , open list , , Mark Bloch , Matt Fleming , Mina Almasry , Nikolay Aleksandrov , "Saeed Mahameed" , Simon Horman , "Stanislav Fomichev" , Stanislav Fomichev , "Tariq Toukan" , William Tu Subject: [PATCH net-next V2 04/13] net/mlx5e: Pre-calculate UMR padding and entry size Date: Tue, 10 Nov 2026 20:38:17 +0200 Message-ID: <20261110183826.2927274-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261110183826.2927274-1-tariqt@nvidia.com> References: <20261110183826.2927274-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF000392D9:EE_|CYXPR12MB9338:EE_ X-MS-Office365-Filtering-Correlation-Id: 86e731ac-65f4-4392-cb65-08df3f59fd65 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|23010399003|56012099006|261026121527099003|261028144727099003|11063799006|261021123027099003|261021121427099003|261022105027099003|261022075727099003|261009223027099003|261026140227099003|261102123227099003|10067099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 6G0I9/9ZgSAwmGyWMIDlK/XI5jFibucU04McTUGXigYIl1nIfFAeqUDoxdH0Yt6sGcaOdUZTt8LGq7rKVwmVVCiZDh2mczXBxS2Oag65ynqgpcurQI47HRb2dQQxtcxXMLShye70xzefQBhXpzSMdL8MzlRmAA0QOsD4r+mDUGsL7KMlTeNrq5ZfY3DJlBhGXRZf4sIh6FmgrRqASgAyn0uLwRYU6pPOsrJf8nRt89PzOjTVFvWdEq1HN+4mfmz6POJE5enGboCD8NCXcwSrp7ChBCQAsJDHcsipplRyYS5c3gMD8yXNNZXLhbSej5IC5wNT5SWkAzJRYLPi+zo+80U6ubWruF2jf5W6VGSOT6Cqo7pRljCsxhQ20EKgDu72e8CF4cWrYgSYxD4wXzRjot6zZGO4DD95O1dquoX3Cp/KwecNYAprG7EkhxxbdRWMgsZE8zFK+GABC8D2MEtOibSsT9OmXouTQfBAo3FRPIkf+GYpVM6aaD5ZM7oKkWq0P/fMZVd4OKoEDvyvj6mV11PCBaKEBj4emvuGLhBhefDG6ow4RR2zWbm7C94Ayb5ZNMvEdGZSw0kDkPt2MTdsTVLJENUW58jrYPQOZxyqXjSkw+t47iEOVj51t+GI0yPDDh00vX+yho2wcEhF2+oLIDApN3CXREGiQFdddp7Q82VcQ99TFuW9lCgzxbNTBVxAtCxIkrSShnFh/BBCeb+zXg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(23010399003)(56012099006)(261026121527099003)(261028144727099003)(11063799006)(261021123027099003)(261021121427099003)(261022105027099003)(261022075727099003)(261009223027099003)(261026140227099003)(261102123227099003)(10067099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6bVJYHnt/CGantwDoTl/0zlyAeQ9frQqMACAPWSb60w5qpk82aiMhzyZn5uEdlbX3Bg8ZINb1bU3DAEBMbHqK7YnNCy/joAlbKozV1R8vTEy7B78XnOhrXUykdknmLDBjyK/O/ndcUGggbbUAqBJAwtED4q2gGvb0U3ZeNnYIMiniycO5guZjkT4447Dj1sUa0I9gYfxjV4kxzzSdpu0/N2/rZRfeqRYiBeGtuqUPqbpHC841eEeCB5Qq4gL5ogoj4hLiPI0aH7tZBE+q285SptdRS8habyCTkYog4BkO3UR1Vt9sfAPt5iErPiXAoB/LboRWhwdNE0CuABXNptsyPCbqDN+PQRDMr3vcDv5PGRym8qjL68gP0eGILcRhWe0eq4xqSl0vhEwUA2Yaw8AlfQ7p1MQ1h4UEDfnAV6zAHxVJfmnHWs1O78L9cz+CBkE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 18:39:44.4791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86e731ac-65f4-4392-cb65-08df3f59fd65 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF000392D9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9338 From: Dragos Tatulea A future patch will add KSM UMRs alongside MTT UMRs for data direct. To avoid additional ifs in the datapath, pre-calculate the UMR padding and entry size based on the UMR mode of the RQ. An additional side benefit is that the padding check from mlx5e_alloc_rx_mpwqe() is no longer needed. This patch doesn't introduce any functional changes. The mlx5e_rq struct doesn't grow because the new members were added in a hole. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 +++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 11 +++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 16 ++++++---------- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index 78cf6aedd04d..000493f42912 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -696,6 +696,9 @@ struct mlx5e_rq { u8 umr_wqebbs; u8 mtts_per_wqe; u8 umr_mode; + u8 umr_entry_size; + u8 umr_pad_bytes; + u16 umr_pad_offset; struct mlx5e_mpw_linear_info *linear_info; struct mlx5e_shampo_hd *shampo; } mpwqe; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 1993da0fdb91..96b521d8bed3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -901,6 +901,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, void *rqc_wq = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); struct mlx5_core_dev *mdev = rq->mdev; u32 pool_order = 0; + u16 entries_bytes; u32 pool_size; int wq_sz; int err; @@ -947,6 +948,16 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); + rq->mpwqe.umr_entry_size = + mlx5e_mpwrq_umr_entry_size(rq->mpwqe.umr_mode); + entries_bytes = rq->mpwqe.pages_per_wqe * + rq->mpwqe.umr_entry_size; + rq->mpwqe.umr_pad_offset = entries_bytes; + /* padding can be 0 when no padding is needed */ + rq->mpwqe.umr_pad_bytes = + ALIGN(entries_bytes, MLX5_UMR_FLEX_ALIGNMENT) - + entries_bytes; + pool_size = rq->mpwqe.pages_per_wqe << mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo); pool_order = rq->mpwqe.page_shift - PAGE_SHIFT; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 22fea4739a2c..a9392ee5376e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -675,16 +675,11 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) }; } - /* Pad if needed, in case the value set to ucseg->xlt_octowords - * in mlx5e_build_umr_wqe() needed alignment. + /* Pad when the value set to ucseg->xlt_octowords in + * mlx5e_build_umr_wqe() needed alignment. */ - if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) { - int pad = ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT) - - rq->mpwqe.pages_per_wqe; - - memset(&umr_wqe->inline_mtts[rq->mpwqe.pages_per_wqe], 0, - sizeof(*umr_wqe->inline_mtts) * pad); - } + memset((u8 *)umr_wqe->inline_mtts + rq->mpwqe.umr_pad_offset, 0, + rq->mpwqe.umr_pad_bytes); bitmap_zero(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); wi->consumed_strides = 0; @@ -693,7 +688,8 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | MLX5_OPCODE_UMR); - offset = (ix * rq->mpwqe.mtts_per_wqe) * sizeof(struct mlx5_mtt) / MLX5_OCTWORD; + offset = ix * rq->mpwqe.mtts_per_wqe * + rq->mpwqe.umr_entry_size / MLX5_OCTWORD; umr_wqe->hdr.uctrl.xlt_offset = cpu_to_be16(offset); sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { -- 2.44.0