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Tue, 10 Nov 2026 10:39:50 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 10 Nov 2026 10:39:42 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Bobby Eshleman , Carolina Jubran , Cosmin Ratiu , Daniel Borkmann , David Wei , Dragos Tatulea , Erfan Sharafzadeh , Gal Pressman , Jacob Keller , Kaifeng Wang , Leon Romanovsky , open list , , Mark Bloch , Matt Fleming , Mina Almasry , Nikolay Aleksandrov , "Saeed Mahameed" , Simon Horman , "Stanislav Fomichev" , Stanislav Fomichev , "Tariq Toukan" , William Tu Subject: [PATCH net-next V2 08/13] net/mlx5e: Add data direct TX infrastructure Date: Tue, 10 Nov 2026 20:38:21 +0200 Message-ID: <20261110183826.2927274-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261110183826.2927274-1-tariqt@nvidia.com> References: <20261110183826.2927274-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH2PEPF00048912:EE_|CH3PR12MB9313:EE_ X-MS-Office365-Filtering-Correlation-Id: 55ad4427-0f69-495c-5def-08df3f5a0c8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700016|23010399003|261102123227099003|261021135927099003|11063799006|261021121427099003|261021123027099003|261026140227099003|261022105027099003|261009223027099003|56012099006|261026121527099003|261028144727099003|18002099003|22082099003|10067099003; X-Microsoft-Antispam-Message-Info: WHgleWcYPMc3hBxhtGog+AkJ3lGyBt5vCQynR4eHtrcASY//qeO1FgKY4jRKKai/04AFbPsVs7XFkrLYXU+09cDacTGS+qvRsS0+5nR0yjU9BurLffkR7ZtHz28/G0eJ2eqxilLdvRxxIFwlU0NSUhIF+e6luBtqEd/RCpfW0UCjzE7DblFalLbE/k0xZJ9rSHp8/8RM50JTRdSq6KkZ5iTYCK/j8iWpCE7amkdFzl9MM6h4YPO37+q3rRBUK6STq4CdaiNflJAcgarLSx5oYxVX4+Tu23fWv2V5TfUggS+BZ1A9liJo6vAKoNprSpK6Z0aa2uZrxmsuFhotSp0iY3ErmIxSFTs/D4yQoX/6zOZUthpJ+q6tXm3bZT24Z3iYmsucloZtDe65T2TGQtHQTSKJX8VoN07imBkwNU62ucIlaTVOUN03NkU+QOhs3iUA6UFZfjyFfuJoAELEWgA3qIFyuCXB51PbWc1HigpqVWMEyjrHt8cY/Qa7LItUscwdL88i1WbAzq/NBnZCpOklsASpgBrxv9dM3Z9xwM/foAQyZLyWusSYXQprUfzdTo2NSOReRtoQDhiAJbWe0xNwpUNs8oc4hGK79ju7VJRzXeEWDVovQA8mlCVZBvS1+8GUMvSvFjumaU39ox2NoKioA6OH+3blUsaag6KdExqs690JgBTuedLLNCuarNGSvNkFV5DAFtgvfufiAOuZTFQMDw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700016)(23010399003)(261102123227099003)(261021135927099003)(11063799006)(261021121427099003)(261021123027099003)(261026140227099003)(261022105027099003)(261009223027099003)(56012099006)(261026121527099003)(261028144727099003)(18002099003)(22082099003)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 40BbiJjkyGflUEpVgtDkz1L4hwU+XVjMq7GlRHmUDRadHPCd9FeccCTy4CzfCAIuucNAfwHUaaLUU6Munq//9lYf/o/MiQmznMQq6HbgkKaX0BQ8r2+u5JYjcIz0fE3T3m3JTrA7QoUh1mk42B6lgkUyZf6gKDtFCp2UAoh/oqIC5aW1gD/g3h1/IKSjHdS+ktWgk2oiPKrDKkIPoEdLSt0APx82QkhhzWzpbdtZIyd9/+8lKR8Q8/o38rU2IhYZamJi3o4K9zUM3qN2mMX2HN9KIFAKl4YlDblaX2eMe6jwth/WClymdccP3BxwOp1VKdls9E7xRnp9UeqSR+FbK8MaRNO+sgpSBWH2FDg1+jjNZgGsaJtJBcPR7cwhbC6nBDXXBVnduyDxo4TVEdrPDTblxee77uWkdH/XHxT9YJSca33UIjKicaoNXintBJTb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 18:40:09.9133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55ad4427-0f69-495c-5def-08df3f5a0c8d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH2PEPF00048912.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9313 From: Dragos Tatulea Data direct is a HW feature that allows a type of peer-to-peer DMA between the NIC and another device (e.g. GPU) going through a specific PCIe topology. For data direct to work on the TX path, a crossing mkey is necessary which is created as a mlx5e resource. This mkey is used by all SQs. For simplicity always create this resource and link it to the SQ if data direct is supported. An SQ state flag is added as well to signal to the TX data path that data direct is enabled. This commit has no functional changes. data direct mode will be enabled in a subsequent commit and mlx5e_queue_get_dma_dev() will then point to the right device. The data_direct private flag is not propagated to PTP SQs because the queue selector will direct devmem net_iovs to regular SQs. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 + .../mellanox/mlx5/core/en/reporter_tx.c | 1 + .../ethernet/mellanox/mlx5/core/en_common.c | 38 ++++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/en_main.c | 6 +++ .../net/ethernet/mellanox/mlx5/core/en_tx.c | 4 +- include/linux/mlx5/driver.h | 1 + 6 files changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index d716e70c6d47..23e45e87cdee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -397,6 +397,7 @@ enum { MLX5E_SQ_STATE_PENDING_XSK_TX, MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, MLX5E_SQ_STATE_LOCK_NEEDED, + MLX5E_SQ_STATE_DATA_DIRECT, /* set when the sq maps net_iov frags through data direct */ MLX5E_NUM_SQ_STATES, /* Must be kept last */ }; @@ -453,6 +454,7 @@ struct mlx5e_txqsq { u8 min_inline_mode; struct device *pdev; __be32 mkey_be; + __be32 crossing_mkey_be; unsigned long state; unsigned int hw_mtu; struct mlx5_clock *clock; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index 8409ae73768f..b4a4ff877bbc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -18,6 +18,7 @@ static const char * const sq_sw_state_type_name[] = { [MLX5E_SQ_STATE_PENDING_XSK_TX] = "pending_xsk_tx", [MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC] = "pending_tls_rx_resync", [MLX5E_SQ_STATE_LOCK_NEEDED] = "lock_needed", + [MLX5E_SQ_STATE_DATA_DIRECT] = "data_direct", }; static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c index c2d4bae533de..c1d3b2ba1864 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -30,6 +30,8 @@ * SOFTWARE. */ +#include + #include "devlink.h" #include "en.h" #include "lib/crypto.h" @@ -153,6 +155,30 @@ mlx5e_get_devlink_param_num_doorbells(struct mlx5_core_dev *dev) return err ? MLX5_DEFAULT_NUM_DOORBELLS : val.vu32; } +static int mlx5e_create_data_direct_crossing_mkey(struct mlx5_core_dev *mdev) +{ + struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; + + if (!mdev->data_direct || + !MLX5_CAP_GEN(mdev, crossing_vhca_mkey)) + return 0; + + return mlx5e_create_crossing_vhca_mkey(mdev, mdev->data_direct->mkey, + U64_MAX, + &res->data_direct_crossing_mkey); +} + +static void mlx5e_destroy_data_direct_crossing_mkey(struct mlx5_core_dev *mdev) +{ + struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; + + if (!mdev->data_direct || + !MLX5_CAP_GEN(mdev, crossing_vhca_mkey)) + return; + + mlx5_core_destroy_mkey(mdev, res->data_direct_crossing_mkey); +} + int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises) { struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; @@ -177,12 +203,19 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises) goto err_dealloc_transport_domain; } + err = mlx5e_create_data_direct_crossing_mkey(mdev); + if (err) { + mlx5_core_err(mdev, "create data direct crossing mkey failed, %d\n", + err); + goto err_destroy_mkey; + } + num_doorbells = min(mlx5e_get_devlink_param_num_doorbells(mdev), mlx5e_get_max_num_channels(mdev)); res->bfregs = kzalloc_objs(*res->bfregs, num_doorbells); if (!res->bfregs) { err = -ENOMEM; - goto err_destroy_mkey; + goto err_destroy_crossing_mkey; } for (i = 0; i < num_doorbells; i++) { @@ -221,6 +254,8 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises) for (i = 0; i < res->num_bfregs; i++) mlx5_free_bfreg(mdev, res->bfregs + i); kfree(res->bfregs); +err_destroy_crossing_mkey: + mlx5e_destroy_data_direct_crossing_mkey(mdev); err_destroy_mkey: mlx5_core_destroy_mkey(mdev, res->mkey); err_dealloc_transport_domain: @@ -241,6 +276,7 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) for (unsigned int i = 0; i < res->num_bfregs; i++) mlx5_free_bfreg(mdev, res->bfregs + i); kfree(res->bfregs); + mlx5e_destroy_data_direct_crossing_mkey(mdev); mlx5_core_destroy_mkey(mdev, res->mkey); mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); mlx5_core_dealloc_pd(mdev, res->pdn); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index cee73f3b7a99..5b99099e4ed0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1825,6 +1825,12 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); if (param->is_mpw) set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); + if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_DATA_DIRECT)) { + u32 mkey = mdev->mlx5e_res.hw_objs.data_direct_crossing_mkey; + + sq->crossing_mkey_be = cpu_to_be32(mkey); + set_bit(MLX5E_SQ_STATE_DATA_DIRECT, &sq->state); + } sq->stop_room = param->stop_room; sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c index 14479da98f42..62ffb41a64df 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -182,6 +182,7 @@ mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb, unsigned char *skb_data, u16 headlen, struct mlx5_wqe_data_seg *dseg) { + bool dd = test_bit(MLX5E_SQ_STATE_DATA_DIRECT, &sq->state); dma_addr_t dma_addr = 0; u8 num_dma = 0; int i; @@ -211,7 +212,8 @@ mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb, goto dma_unmap_wqe_err; dseg->addr = cpu_to_be64(dma_addr); - dseg->lkey = sq->mkey_be; + dseg->lkey = dd && skb_frag_is_net_iov(frag) ? + sq->crossing_mkey_be : sq->mkey_be; dseg->byte_count = cpu_to_be32(fsz); mlx5e_dma_push_netmem(sq, skb_frag_netmem(frag), dma_addr, fsz); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index abb99371ff13..4c8b447337f1 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -678,6 +678,7 @@ struct mlx5e_resources { u32 pdn; struct mlx5_td td; u32 mkey; + u32 data_direct_crossing_mkey; struct mlx5_sq_bfreg *bfregs; unsigned int num_bfregs; #define MLX5_MAX_NUM_TC 8 -- 2.44.0