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Tue, 10 Nov 2026 10:50:45 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 10 Nov 2026 10:50:39 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Alexei Starovoitov , , "Carolina Jubran" , Cosmin Ratiu , "Daniel Borkmann" , Dragos Tatulea , "Gal Pressman" , Jesper Dangaard Brouer , "John Fastabend" , Leon Romanovsky , "open list" , , "Li RongQing" , Mark Bloch , "Richard Cochran" , Saeed Mahameed , Shahar Shitrit , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 2/2] net/mlx5e: Batch ICOSQ trigger RCU synchronization Date: Tue, 10 Nov 2026 20:50:05 +0200 Message-ID: <20261110185005.2932568-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261110185005.2932568-1-tariqt@nvidia.com> References: <20261110185005.2932568-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF0000000C:EE_|DS4PR12MB733313:EE_ X-MS-Office365-Filtering-Correlation-Id: 17c6426a-1228-4b48-d970-08df3f5ba5f9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|7416014|23010399003|18002099003|22082099003|6133799003|10067099003|11063799006|261009223027099003|261028144727099003|261026140227099003|261102123227099003|261021121427099003|261022105027099003|56012099006|261021123027099003|261022113327099003|261022075727099003; X-Microsoft-Antispam-Message-Info: dIxhuCbHlnNvl5qYgLbR71al5rdByeUjHxEaS/BiQ2bTP7Jdj87c6uPXjKl9wnWNAcKlyzgt5L96xhm5xxAz0KeuFqQJpJSOgNGBOGiqYz9KCEw1FlslRy84qXc0RuHPeKCk97Y10TyKTSH//HzcEdQn+4Q53WVFK0aWGaUqLkKRZI2VFuYWqkBnQ+FVYfSo63inG3rsk1qaNJNLSVPeeYhXc/Sp8dFs2vdH5LOjWKATpMsT1HLO3UqBCeRf4mzuKLSBvXue7sjus8wITTlhgXfXHjXxWzIWaQ8yShCaWvJeVpYY87rXTl0GgeWoS5ion8rLEZqwoB/4yN1NePlnu+J/VhGDrd2zohHPb8GAQYO/5VMljLih08oPvnTVN2GA2r7NmfSM3xSoiHZHveaO9jQigUeCrhwsuB773W1A80klC/rRgW5ujmTi7gp3pGMhWCIRLL8eb2/CHEU2gdotapNCc3LIuahXSWpp0bJSW6wVO/ANAMMYCzdci566paVAMtfOcFJ5+6lzvvsOgpxO+1BpW6IZoriBChZPMrjFyJdGB0bq6KAa2wlC6rjeGQgv4xzWJpj7Vae/zcAiDPYmjuorZYL6/JM+MB8JiftjPnCZw2nulct80rksUasPS/FETcLCFCM7MoGZp34bpg9/MWi6Qoid7Y46fFF8kQmU8Y0ydyzW5yRuvgbGzsX6BK1ixidBQhiNEhQyW7JHbLtHaQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(7416014)(23010399003)(18002099003)(22082099003)(6133799003)(10067099003)(11063799006)(261009223027099003)(261028144727099003)(261026140227099003)(261102123227099003)(261021121427099003)(261022105027099003)(56012099006)(261021123027099003)(261022113327099003)(261022075727099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ojph21dhJ/IM44LrGF+D/R3fhxpS5EkvY7oxB2IWQCVSdlOLPs2cvBPasYaPIoatpGudNNEPRNGIKySyOIHMnTiC9AOhADi1a0fwWHa+dez5sdGB/DjB+TmbNDhabGkpEUSANHcT0gAM6fy12E4XCq2d4rAQPl9v5MEY33+nDo2o4ZjWBRiqu8ll5rgHQpD/UZkXMHyzgnUBLx+wP6nAz0R4uhPgAsIQ+83J3mxDpN5fLYVIeilYZh/P9hAi3qj/xI2VIuo+IJvEXMXI53Nfsitz4C1DI3aR20B/9qpdjajYucbCqlltFMqDihF5W9h189A93rXAPuKDR4DSmp/hxgSEIMtjU7TzDulD2txbKl7a467aT3KUyh3fi1PE5vmBw3qr2gHbzWSEpOi1EzmMR0NkXHDhJpSSJg4gJzHsfTavgB2pVtS8HIJSmR954/BS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 18:51:36.8050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17c6426a-1228-4b48-d970-08df3f5ba5f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB733313 From: Carolina Jubran During channel activation, mlx5e_activate_channels() triggers the ICOSQ once for every channel in order to kick NAPI. mlx5e_trigger_napi_icosq() sets MLX5E_SQ_STATE_LOCK_NEEDED and waits for an RCU grace period before serializing the trigger with ICOSQ users in NAPI context. Mark all channel ICOSQs as requiring locking first, wait for a single grace period, and then trigger all of them. Keep mlx5e_trigger_napi_icosq() with its existing synchronization semantics for standalone callers. 248 channels, rcu_normal=1, ip link set eth2 up: Before: 3.095s After: 1.794s (~1.7x faster) Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 28 +++++++++++++++---- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 73b504ba8c8c..0726c42290b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2837,14 +2837,11 @@ static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu) return 0; } -void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) +static void mlx5e_trigger_napi_icosq_post_sync(struct mlx5e_channel *c) { struct mlx5e_icosq *sq = &c->icosq; bool locked; - set_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &sq->state); - synchronize_net(); - locked = mlx5e_icosq_sync_lock(sq); mlx5e_trigger_irq(sq); mlx5e_icosq_sync_unlock(sq, locked); @@ -2852,6 +2849,13 @@ void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) clear_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &sq->state); } +void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) +{ + set_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &c->icosq.state); + synchronize_net(); + mlx5e_trigger_napi_icosq_post_sync(c); +} + void mlx5e_trigger_napi_async_icosq(struct mlx5e_channel *c) { struct mlx5e_icosq *sq = c->async_icosq; @@ -3105,6 +3109,19 @@ int mlx5e_open_channels(struct mlx5e_priv *priv, return err; } +static void mlx5e_trigger_napi_icosqs(struct mlx5e_channels *chs) +{ + int i; + + for (i = 0; i < chs->num; i++) + set_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &chs->c[i]->icosq.state); + + synchronize_net(); + + for (i = 0; i < chs->num; i++) + mlx5e_trigger_napi_icosq_post_sync(chs->c[i]); +} + static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs) { int i; @@ -3115,8 +3132,7 @@ static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channe if (priv->htb) mlx5e_qos_activate_queues(priv); - for (i = 0; i < chs->num; i++) - mlx5e_trigger_napi_icosq(chs->c[i]); + mlx5e_trigger_napi_icosqs(chs); if (chs->ptp) mlx5e_ptp_activate_channel(chs->ptp); -- 2.44.0