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Tue, 10 Nov 2026 20:26:10 +0000 From: Ali Rouhi To: "jiri@resnulli.us" CC: "vadim.fedorenko@linux.dev" , "arkadiusz.kubalewski@intel.com" , "ivecera@redhat.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "cjubran@nvidia.com" , "Oleg.Zadorozhnyi@devoxsoftware.com" , "prabhakar.mahadev-lad.rj@bp.renesas.com" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH net-next v15 01/13] dpll: omit pin phase attributes the driver has no value for Thread-Topic: [PATCH net-next v15 01/13] dpll: omit pin phase attributes the driver has no value for Thread-Index: AQHdcVG4rpCqv+y1wUaqsUhtvrCr3w== Date: Tue, 10 Nov 2026 20:26:09 +0000 Message-ID: <20261110202607.55744-2-arouhi@sitime.com> References: <20261110202607.55744-1-arouhi@sitime.com> In-Reply-To: <20261110202607.55744-1-arouhi@sitime.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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From: Oleg Zadorozhnyi =0A= =0A= Let phase_offset_get and phase_adjust_get return -ENODATA for a pin the=0A= driver has no value for, and leave DPLL_A_PIN_PHASE_OFFSET and=0A= DPLL_A_PIN_PHASE_ADJUST out of the message in that case, as=0A= dpll_msg_add_ffo() already does for the fractional frequency offset.=0A= Today any error from either callback fails the whole pin dump.=0A= =0A= A driver that measures the phase offset only on the input its PLL=0A= tracks, or whose part holds a delay larger than the s32 the adjust=0A= attribute carries, has no value to report for the pin, and a zero=0A= cannot be told from a measurement. A phase adjust request on such a=0A= pin is passed to the driver without the comparison against the old=0A= value, so the delay can still be set or cleared.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Signed-off-by: Ali Rouhi =0A= ---=0A= drivers/dpll/dpll_netlink.c | 14 ++++++++++----=0A= 1 file changed, 10 insertions(+), 4 deletions(-)=0A= =0A= diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c=0A= index e5380d95f238..acf71a93f230 100644=0A= --- a/drivers/dpll/dpll_netlink.c=0A= +++ b/drivers/dpll/dpll_netlink.c=0A= @@ -388,8 +388,11 @@ dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, str= uct dpll_pin *pin,=0A= ret =3D ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),=0A= dpll, dpll_priv(dpll),=0A= &phase_adjust, extack);=0A= - if (ret)=0A= + if (ret) {=0A= + if (ret =3D=3D -ENODATA)=0A= + return 0;=0A= return ret;=0A= + }=0A= if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))=0A= return -EMSGSIZE;=0A= =0A= @@ -411,8 +414,11 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct = dpll_pin *pin,=0A= ret =3D ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),=0A= dpll, dpll_priv(dpll), &phase_offset,=0A= extack);=0A= - if (ret)=0A= + if (ret) {=0A= + if (ret =3D=3D -ENODATA)=0A= + return 0;=0A= return ret;=0A= + }=0A= if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),=0A= &phase_offset, DPLL_A_PIN_PAD))=0A= return -EMSGSIZE;=0A= @@ -1452,11 +1458,11 @@ dpll_pin_phase_adj_set(struct dpll_pin *pin, struct= nlattr *phase_adj_attr,=0A= ret =3D ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),=0A= dpll, dpll_priv(dpll), &old_phase_adj,=0A= extack);=0A= - if (ret) {=0A= + if (ret && ret !=3D -ENODATA) {=0A= NL_SET_ERR_MSG(extack, "unable to get old phase adjust value");=0A= return ret;=0A= }=0A= - if (phase_adj =3D=3D old_phase_adj)=0A= + if (!ret && phase_adj =3D=3D old_phase_adj)=0A= return 0;=0A= =0A= ret =3D ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin),=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=