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Tue, 10 Nov 2026 20:26:14 +0000 From: Ali Rouhi To: "jiri@resnulli.us" CC: "vadim.fedorenko@linux.dev" , "arkadiusz.kubalewski@intel.com" , "ivecera@redhat.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "cjubran@nvidia.com" , "Oleg.Zadorozhnyi@devoxsoftware.com" , "prabhakar.mahadev-lad.rj@bp.renesas.com" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH net-next v15 05/13] dpll: sit9531x: read DPLL types and pin properties from system firmware Thread-Topic: [PATCH net-next v15 05/13] dpll: sit9531x: read DPLL types and pin properties from system firmware Thread-Index: AQHdcVG6os7n7zdz2k+870xKcjJwIQ== Date: Tue, 10 Nov 2026 20:26:12 +0000 Message-ID: <20261110202607.55744-6-arouhi@sitime.com> References: <20261110202607.55744-1-arouhi@sitime.com> In-Reply-To: <20261110202607.55744-1-arouhi@sitime.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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From: Oleg Zadorozhnyi =0A= =0A= Read the DPLL type and, for each pin, its label, direction, capabilities=0A= and supported frequencies from the firmware node, with defaults for a=0A= node that gives none.=0A= =0A= Inputs are the P and N lanes of four pairs: a pair run single-ended=0A= gives two inputs, a differential pair one. Outputs are labeled OUTn by=0A= the driver's index, while reg stays the die slot the binding defines, so=0A= one binding serves both variants.=0A= =0A= An output with no supported-frequencies-hz is advertised as a continuous=0A= range, since the core refuses every frequency request on a pin with=0A= none.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Signed-off-by: Ali Rouhi =0A= ---=0A= drivers/dpll/sit9531x/Makefile | 2 +-=0A= drivers/dpll/sit9531x/core.h | 56 ++++++=0A= drivers/dpll/sit9531x/prop.c | 327 +++++++++++++++++++++++++++++++++=0A= drivers/dpll/sit9531x/prop.h | 37 ++++=0A= 4 files changed, 421 insertions(+), 1 deletion(-)=0A= create mode 100644 drivers/dpll/sit9531x/prop.c=0A= create mode 100644 drivers/dpll/sit9531x/prop.h=0A= =0A= diff --git a/drivers/dpll/sit9531x/Makefile b/drivers/dpll/sit9531x/Makefil= e=0A= index a221fe55386a..819af61123f5 100644=0A= --- a/drivers/dpll/sit9531x/Makefile=0A= +++ b/drivers/dpll/sit9531x/Makefile=0A= @@ -1,4 +1,4 @@=0A= # SPDX-License-Identifier: GPL-2.0-only=0A= =0A= obj-$(CONFIG_SIT9531X_DPLL) +=3D sit9531x.o=0A= -sit9531x-y :=3D core.o=0A= +sit9531x-y :=3D core.o prop.o=0A= diff --git a/drivers/dpll/sit9531x/core.h b/drivers/dpll/sit9531x/core.h=0A= index 0f826313eff8..7a81c9b14b7f 100644=0A= --- a/drivers/dpll/sit9531x/core.h=0A= +++ b/drivers/dpll/sit9531x/core.h=0A= @@ -23,7 +23,15 @@=0A= =0A= #define SIT9531X_NUM_PLLS 4=0A= #define SIT9531X_MAX_INPUTS 8=0A= +#define SIT9531X_NUM_INPUT_PAIRS (SIT9531X_MAX_INPUTS / 2)=0A= #define SIT9531X_MAX_OUTPUTS 12=0A= +/*=0A= + * INTSYNC, the inter-PLL sync line, is two pins: an input pin on the PLL = that=0A= + * locks to it, numbered after the inputs and the xtal, and an output pin = on the=0A= + * PLL that drives it, numbered after the outputs.=0A= + */=0A= +#define SIT9531X_INTSYNC_PIN_ID (SIT9531X_MAX_INPUTS + 1)=0A= +#define SIT9531X_INTSYNC_OUT_PIN_ID SIT9531X_MAX_OUTPUTS=0A= =0A= /*=0A= * struct sit9531x_chip_info - chip variant identification=0A= @@ -41,6 +49,35 @@ struct sit9531x_chip_info {=0A= const u8 *clkout_map;=0A= };=0A= =0A= +/*=0A= + * enum sit9531x_signal_mode - input signal electrical mode=0A= + * @SIT9531X_MODE_SE: single-ended=0A= + * @SIT9531X_MODE_DE: differential=0A= + */=0A= +enum sit9531x_signal_mode {=0A= + SIT9531X_MODE_SE =3D 0,=0A= + SIT9531X_MODE_DE,=0A= +};=0A= +=0A= +/*=0A= + * struct sit9531x_ref - input reference state=0A= + * @freq: configured frequency in Hz=0A= + * @sig_mode: signal mode of the input pair, read from CLKINx_INPUT_MODE a= t=0A= + * probe=0A= + */=0A= +struct sit9531x_ref {=0A= + u64 freq;=0A= + enum sit9531x_signal_mode sig_mode;=0A= +};=0A= +=0A= +/*=0A= + * struct sit9531x_out - output state=0A= + * @freq: output frequency in Hz=0A= + */=0A= +struct sit9531x_out {=0A= + u64 freq;=0A= +};=0A= +=0A= /*=0A= * struct sit9531x_dev - SiT9531x device instance=0A= * @dev: parent device=0A= @@ -51,6 +88,8 @@ struct sit9531x_chip_info {=0A= * @page_lock: held across a page select and its transfer; nests inside=0A= * @multiop_lock=0A= * @page: current page, -1 when unknown=0A= + * @ref: input reference states=0A= + * @out: output states=0A= * @xtal_freq: crystal frequency in Hz=0A= * @reset_gpio: optional reset line, NULL if absent=0A= */=0A= @@ -65,11 +104,28 @@ struct sit9531x_dev {=0A= struct mutex page_lock;=0A= int page;=0A= =0A= + struct sit9531x_ref ref[SIT9531X_MAX_INPUTS + 1]; /* +1 for xtal */=0A= + struct sit9531x_out out[SIT9531X_MAX_OUTPUTS];=0A= u32 xtal_freq;=0A= =0A= struct gpio_desc *reset_gpio;=0A= };=0A= =0A= +/*=0A= + * Input index 2n is the P lane and 2n + 1 the N lane of pair n; index=0A= + * SIT9531X_MAX_INPUTS is the XO.=0A= + */=0A= +=0A= +static inline u8 sit9531x_input_pair(u8 index)=0A= +{=0A= + return index >> 1;=0A= +}=0A= +=0A= +static inline bool sit9531x_input_is_n(u8 index)=0A= +{=0A= + return index & 1;=0A= +}=0A= +=0A= /* Register page of PLL @pll_idx (0 =3D PLLA, 3 =3D PLLD). */=0A= static inline u8 sit9531x_pll_page(u8 pll_idx)=0A= {=0A= diff --git a/drivers/dpll/sit9531x/prop.c b/drivers/dpll/sit9531x/prop.c=0A= new file mode 100644=0A= index 000000000000..b9405eba49a3=0A= --- /dev/null=0A= +++ b/drivers/dpll/sit9531x/prop.c=0A= @@ -0,0 +1,327 @@=0A= +// SPDX-License-Identifier: GPL-2.0=0A= +/*=0A= + * SiTime SiT9531x firmware node property parsing=0A= + *=0A= + * Copyright (C) 2026 SiTime Corp.=0A= + * Author: Ali Rouhi =0A= + * Author: Oleg Zadorozhnyi =0A= + *=0A= + * Retrieves pin properties from Device Tree firmware nodes (or=0A= + * applies defaults when no firmware node exists).=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include "core.h"=0A= +#include "prop.h"=0A= +=0A= +static void sit9531x_input_pin_label(struct sit9531x_dev *sitdev,=0A= + struct sit9531x_pin_props *props, u8 id)=0A= +{=0A= + u8 pair =3D sit9531x_input_pair(id);=0A= +=0A= + if (sitdev->ref[id].sig_mode =3D=3D SIT9531X_MODE_DE)=0A= + snprintf(props->package_label,=0A= + sizeof(props->package_label), "IN%u", pair);=0A= + else=0A= + snprintf(props->package_label,=0A= + sizeof(props->package_label), "IN%u%c", pair,=0A= + sit9531x_input_is_n(id) ? 'N' : 'P');=0A= +}=0A= +=0A= +/* A differential input pair is labeled IN; its N lane is not registere= d. */=0A= +static void=0A= +sit9531x_prop_pin_package_label_set(struct sit9531x_dev *sitdev,=0A= + struct sit9531x_pin_props *props,=0A= + enum dpll_pin_direction dir, u8 id)=0A= +{=0A= + if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT &&=0A= + id =3D=3D SIT9531X_INTSYNC_PIN_ID) {=0A= + strscpy(props->package_label, "INTSYNC",=0A= + sizeof(props->package_label));=0A= + props->dpll_props.package_label =3D props->package_label;=0A= + return;=0A= + }=0A= +=0A= + if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT && id =3D=3D SIT9531X_MAX_INPUTS)= {=0A= + strscpy(props->package_label, "XO",=0A= + sizeof(props->package_label));=0A= + props->dpll_props.package_label =3D props->package_label;=0A= + return;=0A= + }=0A= +=0A= + if (dir =3D=3D DPLL_PIN_DIRECTION_OUTPUT &&=0A= + id =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID) {=0A= + strscpy(props->package_label, "SYNCOUT",=0A= + sizeof(props->package_label));=0A= + props->dpll_props.package_label =3D props->package_label;=0A= + return;=0A= + }=0A= +=0A= + if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT)=0A= + sit9531x_input_pin_label(sitdev, props, id);=0A= + else=0A= + /*=0A= + * Package numbering; on the SiT95317 it differs from the chip=0A= + * slot that the registers and the binding's reg use.=0A= + */=0A= + snprintf(props->package_label, sizeof(props->package_label),=0A= + "OUT%u", id);=0A= +=0A= + props->dpll_props.package_label =3D props->package_label;=0A= +}=0A= +=0A= +/* An output's reg is the chip slot it drives, not the driver's index. */= =0A= +static int=0A= +sit9531x_prop_pin_fwnode_get(struct sit9531x_dev *sitdev,=0A= + struct sit9531x_pin_props *props,=0A= + enum dpll_pin_direction dir, u8 id)=0A= +{=0A= + struct fwnode_handle *pins_node, *pin_node;=0A= + const char *node_name;=0A= +=0A= + if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT) {=0A= + node_name =3D "input-pins";=0A= + } else {=0A= + node_name =3D "output-pins";=0A= + if (id < sitdev->info->num_outputs)=0A= + id =3D sitdev->info->clkout_map[id];=0A= + }=0A= +=0A= + pins_node =3D device_get_named_child_node(sitdev->dev, node_name);=0A= + if (!pins_node) {=0A= + dev_dbg(sitdev->dev, "'%s' sub-node is missing\n", node_name);=0A= + return -ENOENT;=0A= + }=0A= +=0A= + fwnode_for_each_child_node(pins_node, pin_node) {=0A= + u32 reg;=0A= +=0A= + if (fwnode_property_read_u32(pin_node, "reg", ®))=0A= + continue;=0A= +=0A= + if (id =3D=3D reg)=0A= + break;=0A= + }=0A= +=0A= + fwnode_handle_put(pins_node);=0A= +=0A= + props->fwnode =3D pin_node;=0A= +=0A= + dev_dbg(sitdev->dev, "Firmware node for %s %sfound\n",=0A= + props->package_label, pin_node ? "" : "NOT ");=0A= +=0A= + return pin_node ? 0 : -ENOENT;=0A= +}=0A= +=0A= +/* Free the result with sit9531x_pin_props_put(). */=0A= +struct sit9531x_pin_props *=0A= +sit9531x_pin_props_get(struct sit9531x_dev *sitdev,=0A= + enum dpll_pin_direction dir, u8 index)=0A= +{=0A= + bool sync_in =3D dir =3D=3D DPLL_PIN_DIRECTION_INPUT &&=0A= + index =3D=3D SIT9531X_INTSYNC_PIN_ID;=0A= + bool sync_out =3D dir =3D=3D DPLL_PIN_DIRECTION_OUTPUT &&=0A= + index =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID;=0A= + bool xo =3D dir =3D=3D DPLL_PIN_DIRECTION_INPUT &&=0A= + index =3D=3D SIT9531X_MAX_INPUTS;=0A= + struct dpll_pin_frequency *ranges;=0A= + struct sit9531x_pin_props *props;=0A= + int i, j, num_freqs =3D 0, rc;=0A= + u32 *freqs =3D NULL;=0A= + const char *type;=0A= + u64 curr_freq;=0A= +=0A= + props =3D kzalloc_obj(*props, GFP_KERNEL);=0A= + if (!props)=0A= + return ERR_PTR(-ENOMEM);=0A= +=0A= + if (sync_in) {=0A= + /* INTSYNC destination: a reference the PLL can lock to. */=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_INT_OSCILLATOR;=0A= + props->dpll_props.capabilities =3D=0A= + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;=0A= + curr_freq =3D 0;=0A= + } else if (sync_out) {=0A= + /* INTSYNC source: driving it is not a reference selection */=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_INT_OSCILLATOR;=0A= + props->dpll_props.capabilities =3D=0A= + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;=0A= + curr_freq =3D 0;=0A= + } else if (xo) {=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_INT_OSCILLATOR;=0A= + props->dpll_props.capabilities =3D 0;=0A= + curr_freq =3D sitdev->xtal_freq;=0A= + } else if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT) {=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_EXT;=0A= + props->dpll_props.capabilities =3D=0A= + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;=0A= + curr_freq =3D sitdev->ref[index].freq;=0A= + } else {=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_EXT;=0A= + props->dpll_props.capabilities =3D=0A= + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;=0A= + curr_freq =3D 0;=0A= + }=0A= +=0A= + sit9531x_prop_pin_package_label_set(sitdev, props, dir, index);=0A= +=0A= + /* Internal pins take no properties from the firmware node. */=0A= + if (sync_in || sync_out || xo)=0A= + goto skip_fwnode_props;=0A= +=0A= + rc =3D sit9531x_prop_pin_fwnode_get(sitdev, props, dir, index);=0A= + if (rc)=0A= + goto skip_fwnode_props;=0A= +=0A= + fwnode_property_read_string(props->fwnode, "label",=0A= + &props->dpll_props.board_label);=0A= +=0A= + if (!fwnode_property_read_string(props->fwnode, "connection-type",=0A= + &type)) {=0A= + if (!strcmp(type, "ext"))=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_EXT;=0A= + else if (!strcmp(type, "gnss"))=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_GNSS;=0A= + else if (!strcmp(type, "int"))=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_INT_OSCILLATOR;=0A= + else if (!strcmp(type, "synce"))=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_SYNCE_ETH_PORT;=0A= + else if (!strcmp(type, "mux"))=0A= + props->dpll_props.type =3D DPLL_PIN_TYPE_MUX;=0A= + else=0A= + dev_warn(sitdev->dev,=0A= + "Unknown pin type '%s'\n", type);=0A= + }=0A= +=0A= + if (!fwnode_property_present(props->fwnode,=0A= + "supported-frequencies-hz"))=0A= + goto skip_fwnode_props;=0A= +=0A= + /* A -hz property is 32-bit; no rate of this part needs more. */=0A= + num_freqs =3D fwnode_property_count_u32(props->fwnode,=0A= + "supported-frequencies-hz");=0A= + if (num_freqs <=3D 0) {=0A= + rc =3D num_freqs ? num_freqs : -EINVAL;=0A= + dev_err(sitdev->dev,=0A= + "malformed supported-frequencies-hz for %s: %d\n",=0A= + props->package_label, rc);=0A= + goto err_alloc_freqs;=0A= + }=0A= +=0A= + freqs =3D kcalloc(num_freqs, sizeof(*freqs), GFP_KERNEL);=0A= + if (!freqs) {=0A= + rc =3D -ENOMEM;=0A= + goto err_alloc_freqs;=0A= + }=0A= +=0A= + rc =3D fwnode_property_read_u32_array(props->fwnode,=0A= + "supported-frequencies-hz",=0A= + freqs, num_freqs);=0A= + if (rc) {=0A= + dev_warn(sitdev->dev,=0A= + "failed to parse supported-frequencies-hz for %s: %d\n",=0A= + props->package_label, rc);=0A= + goto err_alloc_ranges;=0A= + }=0A= +=0A= + /* The first listed rate seeds the input's rate */=0A= + if (num_freqs > 0 && dir =3D=3D DPLL_PIN_DIRECTION_INPUT && !xo)=0A= + curr_freq =3D freqs[0];=0A= +=0A= +skip_fwnode_props:=0A= + if (sync_in || sync_out)=0A= + return props;=0A= +=0A= + /*=0A= + * An output with no listed rates gets one wide range, as the setter=0A= + * checks Fvco/N; the XO gets its one rate.=0A= + */=0A= + ranges =3D kcalloc(num_freqs + 1, sizeof(*ranges), GFP_KERNEL);=0A= + if (!ranges) {=0A= + rc =3D -ENOMEM;=0A= + goto err_alloc_ranges;=0A= + }=0A= +=0A= + /* Set after the last allocation that can fail */=0A= + if (curr_freq && dir =3D=3D DPLL_PIN_DIRECTION_INPUT)=0A= + sitdev->ref[index].freq =3D curr_freq;=0A= +=0A= + j =3D 0;=0A= +=0A= + for (i =3D 0; i < num_freqs; i++) {=0A= + struct dpll_pin_frequency freq =3D DPLL_PIN_FREQUENCY(freqs[i]);=0A= +=0A= + ranges[j++] =3D freq;=0A= + }=0A= +=0A= + if (!num_freqs && dir =3D=3D DPLL_PIN_DIRECTION_OUTPUT) {=0A= + ranges[j].min =3D 1;=0A= + ranges[j].max =3D 1000000000ULL; /* 1 GHz */=0A= + j++;=0A= + } else if (!num_freqs && curr_freq) {=0A= + struct dpll_pin_frequency f =3D DPLL_PIN_FREQUENCY(curr_freq);=0A= +=0A= + ranges[j++] =3D f;=0A= + }=0A= +=0A= + if (j > 0) {=0A= + props->dpll_props.freq_supported =3D ranges;=0A= + props->dpll_props.freq_supported_num =3D j;=0A= + } else {=0A= + kfree(ranges);=0A= + props->dpll_props.freq_supported =3D NULL;=0A= + props->dpll_props.freq_supported_num =3D 0;=0A= + }=0A= +=0A= + kfree(freqs);=0A= +=0A= + return props;=0A= +=0A= +err_alloc_ranges:=0A= + kfree(freqs);=0A= +err_alloc_freqs:=0A= + fwnode_handle_put(props->fwnode);=0A= + kfree(props);=0A= +=0A= + return ERR_PTR(rc);=0A= +}=0A= +=0A= +void sit9531x_pin_props_put(struct sit9531x_pin_props *props)=0A= +{=0A= + kfree(props->dpll_props.freq_supported);=0A= +=0A= + if (props->fwnode)=0A= + fwnode_handle_put(props->fwnode);=0A= +=0A= + kfree(props);=0A= +}=0A= +=0A= +enum dpll_type=0A= +sit9531x_prop_dpll_type_get(struct sit9531x_dev *sitdev, u8 index)=0A= +{=0A= + const char *types[SIT9531X_NUM_PLLS];=0A= + int count;=0A= +=0A= + count =3D device_property_read_string_array(sitdev->dev, "dpll-types",=0A= + types, ARRAY_SIZE(types));=0A= +=0A= + if (index >=3D count || !types[index])=0A= + return DPLL_TYPE_PPS;=0A= +=0A= + if (!strcmp(types[index], "pps"))=0A= + return DPLL_TYPE_PPS;=0A= + else if (!strcmp(types[index], "eec"))=0A= + return DPLL_TYPE_EEC;=0A= +=0A= + dev_warn(sitdev->dev, "Unknown DPLL type '%s', using default\n",=0A= + types[index]);=0A= +=0A= + return DPLL_TYPE_PPS;=0A= +}=0A= diff --git a/drivers/dpll/sit9531x/prop.h b/drivers/dpll/sit9531x/prop.h=0A= new file mode 100644=0A= index 000000000000..b16db0bc51c6=0A= --- /dev/null=0A= +++ b/drivers/dpll/sit9531x/prop.h=0A= @@ -0,0 +1,37 @@=0A= +/* SPDX-License-Identifier: GPL-2.0 */=0A= +/*=0A= + * SiTime SiT9531x firmware node property parsing=0A= + *=0A= + * Copyright (C) 2026 SiTime Corp.=0A= + * Author: Ali Rouhi =0A= + * Author: Oleg Zadorozhnyi =0A= + */=0A= +=0A= +#ifndef _SIT9531X_PROP_H=0A= +#define _SIT9531X_PROP_H=0A= +=0A= +#include =0A= +#include =0A= +=0A= +struct sit9531x_dev;=0A= +=0A= +/*=0A= + * struct sit9531x_pin_props - pin properties from firmware=0A= + * @fwnode: firmware node handle, NULL if no DT node=0A= + * @dpll_props: DPLL core pin properties=0A= + * @package_label: pin package label (e.g. "IN0", "OUT3")=0A= + */=0A= +struct sit9531x_pin_props {=0A= + struct fwnode_handle *fwnode;=0A= + struct dpll_pin_properties dpll_props;=0A= + char package_label[8];=0A= +};=0A= +=0A= +enum dpll_type sit9531x_prop_dpll_type_get(struct sit9531x_dev *sitdev,=0A= + u8 index);=0A= +struct sit9531x_pin_props *sit9531x_pin_props_get(struct sit9531x_dev *sit= dev,=0A= + enum dpll_pin_direction dir,=0A= + u8 index);=0A= +void sit9531x_pin_props_put(struct sit9531x_pin_props *props);=0A= +=0A= +#endif /* _SIT9531X_PROP_H */=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=