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Tue, 10 Nov 2026 14:36:57 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37520cfdfadsm11488863eec.19.2026.11.10.14.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 14:36:56 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: macro@orcam.me.uk, Florian Fainelli , Thomas Bogendoerfer , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype Date: Tue, 10 Nov 2026 14:36:49 -0800 Message-ID: <20261110223651.2698860-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following warning: arch/mips/mm/cerr-sb1.c:165:17: warning: no previous prototype for ‘sb1_cache_error’ [-Wmissing-prototypes] 165 | asmlinkage void sb1_cache_error(void) | ^~~~~~~~~~~~~~~ Signed-off-by: Florian Fainelli --- arch/mips/include/asm/sibyte/sb1250.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h index de4b352256c8..e42b3c9f4b53 100644 --- a/arch/mips/include/asm/sibyte/sb1250.h +++ b/arch/mips/include/asm/sibyte/sb1250.h @@ -32,6 +32,8 @@ extern unsigned int soc_type; extern unsigned int periph_rev; extern unsigned int zbbus_mhz; +void sb1_cache_error(void); + extern void sb1250_mask_irq(int cpu, int irq); extern void sb1250_unmask_irq(int cpu, int irq); -- 2.53.0