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From: Jammy Huang <jammy_huang@aspeedtech.com>
To: Dave Airlie <airlied@redhat.com>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Jocelyn Falempe <jfalempe@redhat.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>
Cc: <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
	"Jammy Huang" <jammy_huang@aspeedtech.com>
Subject: [PATCH] drm/ast: Get VRAM size from PCI BAR0
Date: Wed, 11 Nov 2026 14:16:20 +0800	[thread overview]
Message-ID: <20261111-ast-vram-size-from-bar0-v1-1-dff97e2f8ccd@aspeedtech.com> (raw)

ast_get_vram_size() decodes the VRAM size from VGACRAA[1:0]. The size
of PCI BAR0, the framebuffer aperture, already reflects the VGA memory
size configured in hardware, so the separate register lookup is
redundant. Using the BAR size also guarantees that the VRAM mapping
never extends beyond the aperture that the device decodes.

Take the VRAM size from BAR0 and keep subtracting the reserved region
given by VGACR99[1:0].

Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
---
The ast driver currently determines the VRAM size by decoding
VGACRAA[1:0]. Since the size of PCI BAR0 already reflects the VGA
memory size configured in hardware, use it directly and drop the
register lookup. The reserved region reported in VGACR99[1:0] is still
subtracted from the result.
---
 drivers/gpu/drm/ast/ast_mm.c | 27 +++++----------------------
 1 file changed, 5 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_mm.c b/drivers/gpu/drm/ast/ast_mm.c
index 0bc14031946..6ef686cca5b 100644
--- a/drivers/gpu/drm/ast/ast_mm.c
+++ b/drivers/gpu/drm/ast/ast_mm.c
@@ -33,26 +33,10 @@
 
 #include "ast_drv.h"
 
-static u32 ast_get_vram_size(struct ast_device *ast)
+static resource_size_t ast_get_vram_size(struct ast_device *ast, resource_size_t bar_size)
 {
-	u32 vram_size;
-	u8 vgacr99, vgacraa;
-
-	vgacraa = ast_get_index_reg(ast, AST_IO_VGACRI, 0xaa);
-	switch (vgacraa & AST_IO_VGACRAA_VGAMEM_SIZE_MASK) {
-	case 0:
-		vram_size = SZ_8M;
-		break;
-	case 1:
-		vram_size = SZ_16M;
-		break;
-	case 2:
-		vram_size = SZ_32M;
-		break;
-	case 3:
-		vram_size = SZ_64M;
-		break;
-	}
+	resource_size_t vram_size = bar_size;
+	u8 vgacr99;
 
 	vgacr99 = ast_get_index_reg(ast, AST_IO_VGACRI, 0x99);
 	switch (vgacr99 & AST_IO_VGACR99_VGAMEM_RSRV_MASK) {
@@ -74,8 +58,7 @@ int ast_mm_init(struct ast_device *ast)
 {
 	struct drm_device *dev = &ast->base;
 	struct pci_dev *pdev = to_pci_dev(dev->dev);
-	resource_size_t base, size;
-	u32 vram_size;
+	resource_size_t base, size, vram_size;
 
 	base = pci_resource_start(pdev, 0);
 	size = pci_resource_len(pdev, 0);
@@ -84,7 +67,7 @@ int ast_mm_init(struct ast_device *ast)
 	devm_arch_io_reserve_memtype_wc(dev->dev, base, size);
 	devm_arch_phys_wc_add(dev->dev, base, size);
 
-	vram_size = ast_get_vram_size(ast);
+	vram_size = ast_get_vram_size(ast, size);
 
 	ast->vram = devm_ioremap_wc(dev->dev, base, vram_size);
 	if (!ast->vram)

---
base-commit: 067c5c24cef23d913b67eaaf71ae67e7169a6620
change-id: 20261111-ast-vram-size-from-bar0-13819df1df24

Best regards,
-- 
Jammy Huang <jammy_huang@aspeedtech.com>


                 reply	other threads:[~2026-11-11  6:16 UTC|newest]

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