Re: [PATCH v7 1/2] dt-bindings: usb: Add CIX Sky1 USBSSP controller

[Krzysztof Kozlowski <krzk@kernel.org>]

On Fri, Nov 06, 2026 at 06:12:09PM +0800, Hongliang Yang wrote:
> Add device tree binding for the CIX Sky1 Cadence USBSSP controller.
> Each instance wraps one of the two USB3 Type-A DRD controllers of the
> SoC and owns a register range in the USB30 Type-A DRD RCSU block at
> 0x091c0000:
> 
>   offset  register       contents                       controller
>   0x0300  STRAP_PIN0     stream ID (SID/SSID)           USB4
>   0x0304  STRAP_PIN1     stream ID (SID/SSID)           USB5
>   0x030c  STRAP_PIN3     clock enables, ctrl and PHYs   USB4, USB5
>   0x0314  STRAP_PIN5     awcache[3:0], arcache[7:4]     USB4
>   0x0324  STRAP_PIN9     awcache[3:0], arcache[7:4]     USB5
>   0x0328  STRAP_PIN10    USB2 PLL controls              USB4
>   0x0400  STRAP_STATUS0  AXI clock enable/valid/req     USB4
>   0x0410  STRAP_STATUS4  AXI clock enable/valid/req     USB5
> 
> Controller 0 of the block is used by USB4, controller 1 is used by
> USB5. The range of each instance starts at its own AXI cache attribute
> strap register and ends after its own AXI clock status register, so the
> two ranges overlap: the strap and status registers of the two
> controllers are interleaved in the block.
> 
> The Cadence USBSSP core itself is described by a child node at its own
> address. Mode strap controls are programmed through the Sky1 S5 system
> controller referenced by the cix,usb-syscon phandle, whose arguments
> give the register offset and the bit position of the strap field.
> 
> Signed-off-by: Hongliang Yang <hongliang.yang@cixtech.com>
> ---

Unanswered comments from Sashiko, dropping from DT Patchwork.

Best regards,
Krzysztof