Re: [PATCH v2 3/4] dt-bindings: clock: Add Siflower SF19A2890 peripheral clock/reset managers

[Conor Dooley <conor@kernel.org>]

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On Wed, Nov 11, 2026 at 03:19:02AM -0500, Joseph Telaak via B4 Relay wrote:
> From: Joseph Telaak <joseph@telaak.dev>
> 
> Each peripheral block of the Siflower SF19A2890 has a clock and reset
> manager of its own, with a reset register, a clock gate register and a
> bus output enable. The blocks differ in which gate and reset bits they
> use, so each has its own compatible, and clock N of a manager is its
> input clock N, gated. The header names the clocks and resets of each
> manager, since their meaning depends on the manager.
> 
> Based on Chuanhong Guo's binding, which described every block with one
> compatible and its bit layout in properties.
> 
> Signed-off-by: Joseph Telaak <joseph@telaak.dev>

This looks a bit messy with all the different clocks, but I don't think
there's any value in breaking it out to 17 individual files nor is there
anything common really to try to combine conditions etc.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

Cheers,
Conor.

> ---
>  .../clock/siflower,sf19a2890-periph-crm.yaml       | 166 +++++++++++++++++++++
>  MAINTAINERS                                        |   2 +
>  .../clock/siflower,sf19a2890-periph-crm.h          |  87 +++++++++++
>  3 files changed, 255 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml b/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml
> new file mode 100644
> index 000000000000..f464cfffb2a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/siflower,sf19a2890-periph-crm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Siflower SF19A2890 peripheral clock and reset manager
> +
> +maintainers:
> +  - Joseph Telaak <joseph@telaak.dev>
> +
> +description: |
> +  Each peripheral, or group of peripherals, of the Siflower SF19A2890 has
> +  a clock and reset manager of its own: a reset register, a clock gate
> +  register, and a bus output enable that the peripherals need as well as
> +  their clocks to answer bus requests.
> +
> +  Clock N of the manager is input clock N, gated. The clocks and resets of
> +  each manager are defined in
> +  include/dt-bindings/clock/siflower,sf19a2890-periph-crm.h.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - siflower,sf19a2890-gmac-crm
> +      - siflower,sf19a2890-gpio-crm
> +      - siflower,sf19a2890-i2c-crm
> +      - siflower,sf19a2890-pwm-crm
> +      - siflower,sf19a2890-rf-crm
> +      - siflower,sf19a2890-spi-crm
> +      - siflower,sf19a2890-timer-crm
> +      - siflower,sf19a2890-uart-crm
> +      - siflower,sf19a2890-usb-crm
> +      - siflower,sf19a2890-wdt-crm
> +      - siflower,sf19a2890-wlan24-crm
> +      - siflower,sf19a2890-wlan5-crm
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 6
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  "#reset-cells":
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - "#clock-cells"
> +  - "#reset-cells"
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: siflower,sf19a2890-gmac-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: GMAC bus clock
> +            - description: GMAC register clock
> +            - description: RGMII transmit reference clock
> +            - description: Timestamp unit clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - siflower,sf19a2890-wlan24-crm
> +              - siflower,sf19a2890-wlan5-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: AXI slave clock
> +            - description: AXI master clock
> +            - description: Radio platform clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: siflower,sf19a2890-rf-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Test clock
> +            - description: AXI slave clock
> +            - description: Boot clock
> +            - description: Low-power clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: siflower,sf19a2890-usb-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: USB controller clock
> +            - description: AXI master clock
> +            - description: USB PHY reference clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: siflower,sf19a2890-spi-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: APB clock
> +            - description: SSP clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: siflower,sf19a2890-uart-crm
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: UART0 APB clock
> +            - description: UART1 APB clock
> +            - description: UART2 APB clock
> +            - description: UART0 clock
> +            - description: UART1 clock
> +            - description: UART2 clock
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - siflower,sf19a2890-gpio-crm
> +              - siflower,sf19a2890-i2c-crm
> +              - siflower,sf19a2890-pwm-crm
> +              - siflower,sf19a2890-timer-crm
> +              - siflower,sf19a2890-wdt-crm
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/siflower,sf19a2890-clk.h>
> +
> +    clock-controller@19e24c00 {
> +        compatible = "siflower,sf19a2890-uart-crm";
> +        reg = <0x19e24c00 0x10>;
> +        clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>,
> +                 <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_UART>,
> +                 <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>;
> +        #clock-cells = <1>;
> +        #reset-cells = <1>;
> +    };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index de087d1c255d..47a3a72a5d08 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25703,8 +25703,10 @@ M:	Joseph Telaak <joseph@telaak.dev>
>  L:	linux-clk@vger.kernel.org
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/clock/siflower,sf19a2890-clk.yaml
> +F:	Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml
>  F:	drivers/clk/siflower/clk-sf19a2890.c
>  F:	include/dt-bindings/clock/siflower,sf19a2890-clk.h
> +F:	include/dt-bindings/clock/siflower,sf19a2890-periph-crm.h
>  
>  SILEAD TOUCHSCREEN DRIVER
>  M:	Hans de Goede <hansg@kernel.org>
> diff --git a/include/dt-bindings/clock/siflower,sf19a2890-periph-crm.h b/include/dt-bindings/clock/siflower,sf19a2890-periph-crm.h
> new file mode 100644
> index 000000000000..1cf54761fe72
> --- /dev/null
> +++ b/include/dt-bindings/clock/siflower,sf19a2890-periph-crm.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +#ifndef __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_PERIPH_CRM_H
> +#define __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_PERIPH_CRM_H
> +
> +/* siflower,sf19a2890-gmac-crm */
> +#define CLK_GMAC_BUS		0
> +#define CLK_GMAC_REG		1
> +#define CLK_GMAC_TX_REF		2
> +#define CLK_GMAC_TSU		3
> +
> +#define RST_GMAC		0
> +
> +/* siflower,sf19a2890-gpio-crm */
> +#define CLK_GPIO		0
> +
> +#define RST_GPIO		0
> +
> +/* siflower,sf19a2890-i2c-crm */
> +#define CLK_I2C			0
> +
> +#define RST_I2C			0
> +
> +/* siflower,sf19a2890-pwm-crm */
> +#define CLK_PWM			0
> +
> +#define RST_PWM			0
> +
> +/* siflower,sf19a2890-rf-crm */
> +#define CLK_RF_TEST		0
> +#define CLK_RF_AXIS		1
> +#define CLK_RF_BOOT		2
> +#define CLK_RF_LP		3
> +
> +#define RST_RF			0
> +
> +/* siflower,sf19a2890-spi-crm */
> +#define CLK_SPI_APB		0
> +#define CLK_SPI_SSP		1
> +
> +#define RST_SPI			0
> +
> +/* siflower,sf19a2890-timer-crm */
> +#define CLK_TIMER		0
> +
> +#define RST_TIMER		0
> +
> +/* siflower,sf19a2890-uart-crm */
> +#define CLK_UART0_APB		0
> +#define CLK_UART1_APB		1
> +#define CLK_UART2_APB		2
> +#define CLK_UART0		3
> +#define CLK_UART1		4
> +#define CLK_UART2		5
> +
> +#define RST_UART0		0
> +#define RST_UART1		1
> +#define RST_UART2		2
> +
> +/* siflower,sf19a2890-usb-crm */
> +#define CLK_USB			0
> +#define CLK_USB_AXIM		1
> +#define CLK_USB_PHY_REF		2
> +
> +#define RST_USB			0
> +#define RST_USB_PHY_POR		1
> +#define RST_USB_PHY		2
> +
> +/* siflower,sf19a2890-wdt-crm */
> +#define CLK_WDT			0
> +
> +#define RST_WDT			0
> +
> +/* siflower,sf19a2890-wlan24-crm */
> +#define CLK_WLAN24_AXIS		0
> +#define CLK_WLAN24_AXIM		1
> +#define CLK_WLAN24_PLF		2
> +
> +#define RST_WLAN24		0
> +
> +/* siflower,sf19a2890-wlan5-crm */
> +#define CLK_WLAN5_AXIS		0
> +#define CLK_WLAN5_AXIM		1
> +#define CLK_WLAN5_PLF		2
> +
> +#define RST_WLAN5		0
> +
> +#endif /* __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_PERIPH_CRM_H */
> 
> -- 
> Git-155)
> 
> 

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