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Date: Wed, 11 Nov 2026 07:41:51 +0530 Message-Id: <20261111021151.58380-1-parame@synopsys.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261101005243.4739-1-parame@synopsys.com> References: <20261101005243.4739-1-parame@synopsys.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTExMDAwOCBTYWx0ZWRfX4dZE6dKtVxcH 6+hDc5Qwlpv7Wh/Ju16/7txpj0ZuIjIDASx4wpBhkWXLvTxt5UFnp0YpB4RMaMLUo9SVX/0yDyO KOqJcptv7MOExSwNDOl066nxeLvdVlbtOHhFfu2qzYxIg33t+aL8pl6nqlSrXgtxK7/kyyy/eiB LioC9pYdkKKvX+8FYDOHGhu7D8ssPjMHYj5hHNwbtgjGYVK9mmxT3VF0gjWTM7+tYkFOKwOqbVy TDUd/d3i8jgXg3blvszNntGnDXJTC75jJG6OE5AVkvX1lBUOosAM5zYjtwDZf5yonKzsHSQHHAB +t+NCwRyXXa3q2XsZew5iyY2UVA5iIVheWTfX79vhCzAWdTvWR5saWU4j+QBQETVcywck6OrFHr /bXEup3ZPZYycqSzmxDF3nzABtVgBWKLssBsKbNMH1OKycO+oUeOJTPyqfA7RwiMc7BMiGV/4zn ERDxV0uzV1wSTTU6XXg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTExMDAwOCBTYWx0ZWRfX3Bp4I5wFLDMx 3EOSpGMAhr+j2EZ3vlAtELe74hZvYot/7Ai2ZkjUr0BQZg7K/kzLMeeCYhvGJuJsiS5B3Wql2vV NKOuBFd97a3i+K4Lj8ACui51ygLMjZs= X-Authority-Analysis: v=2.4 cv=Y6ptIReN c=1 sm=1 tr=0 ts=6af3ceef cx=c_pps a=8EbXvwLXkpGsT4ql/pYRAw==:117 a=8EbXvwLXkpGsT4ql/pYRAw==:17 a=zJRp6_cAMcgA:10 a=qPHU084jO2kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=tU_645BZ7FZt8VqRJtHG:22 a=jSPayVjLy6xbsuKauFBc:22 a=jIQo8A4GAAAA:8 a=fP0m63MfXcOeATsXSlwA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 X-Proofpoint-GUID: b_Y-wSIjn9MBMccKRU9DVI7H921_fdXq X-Proofpoint-ORIG-GUID: b_Y-wSIjn9MBMccKRU9DVI7H921_fdXq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-11_01,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_active_cloned_notspam policy=outbound_active_cloned score=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611110008 Implement HDR-DDR transfer support for the DesignWare Controller. Only support for private transfers and does not support sending CCC commands in HDR mode. Key differences: - Sets the speed to HDR_DDR_SPEED(6) and COMMAND_PORT_CP to do data transfer in HDR-DDR mode. Hardware will generate the ENTHDR0 based on this. - HDR exit pattern will generated from the hardware when it sees the TOC on HDR-DDR mode. Signed-off-by: Dineshkumar Parameswaran --- changes in v3: - Updated commit message. - Sets the HDR-DDR Read and Write based on cmd. drivers/i3c/master/dw-i3c-master.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index 05584ddaf104..d4a0b1d316a9 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -65,6 +65,8 @@ #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 +#define HDR_DDR_CMD_READ 0x80 + #define RESPONSE_QUEUE_PORT 0x10 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) #define RESPONSE_NO_ERROR 0 @@ -232,6 +234,8 @@ #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 #define I3C_BUS_THIGH_MAX_NS 41 +#define DW_I3C_HDR_DDR_SPEED 6 + #define XFER_TIMEOUT (msecs_to_jiffies(1000)) #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ @@ -381,6 +385,11 @@ static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes); } +static bool dw_cmd_is_read(u32 rnw_cmd, enum i3c_xfer_mode mode) +{ + return (mode == I3C_HDR_DDR) ? (rnw_cmd & HDR_DDR_CMD_READ) : rnw_cmd; +} + static struct dw_i3c_xfer * dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) { @@ -726,6 +735,8 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m) memset(&info, 0, sizeof(info)); info.dyn_addr = ret; + info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR); + ret = i3c_master_set_info(&master->base, &info); if (ret) goto rpm_out; @@ -995,28 +1006,36 @@ static int dw_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, } for (i = 0; i < i3c_nxfers; i++) { + u32 rnw_cmd = (mode == I3C_SDR) ? i3c_xfers[i].rnw : i3c_xfers[i].cmd; + bool rnw = dw_cmd_is_read(rnw_cmd, mode); struct dw_i3c_cmd *cmd = &xfer->cmds[i]; cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | COMMAND_PORT_TRANSFER_ARG; - if (i3c_xfers[i].rnw) { + if (rnw) { cmd->rx_buf = i3c_xfers[i].data.in; cmd->rx_len = i3c_xfers[i].len; - cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | - COMMAND_PORT_SPEED(dev->info.max_read_ds); + cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER; } else { cmd->tx_buf = i3c_xfers[i].data.out; cmd->tx_len = i3c_xfers[i].len; - cmd->cmd_lo = - COMMAND_PORT_SPEED(dev->info.max_write_ds); } cmd->cmd_lo |= COMMAND_PORT_TID(i) | COMMAND_PORT_DEV_INDEX(data->index) | COMMAND_PORT_ROC; + if (mode == I3C_HDR_DDR) { + cmd->cmd_lo |= COMMAND_PORT_CMD(rnw_cmd) | COMMAND_PORT_CP | + COMMAND_PORT_SPEED(DW_I3C_HDR_DDR_SPEED); + } else { + cmd->cmd_lo |= (i3c_xfers[i].rnw) ? + COMMAND_PORT_SPEED(dev->info.max_read_ds) : + COMMAND_PORT_SPEED(dev->info.max_write_ds); + } + if (i == (i3c_nxfers - 1)) cmd->cmd_lo |= COMMAND_PORT_TOC; } -- 2.34.1