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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF00022BCD.mail.protection.outlook.com (10.167.248.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Wed, 11 Nov 2026 05:40:56 +0000 Received: from dcsm-trdripper1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Tue, 10 Nov 2026 23:40:53 -0600 From: Akshay Gupta To: , CC: , , , , , , , , Prathima Lk , Akshay Gupta Subject: [PATCH v1 1/3] misc: amd-sbi: use sized DMA-safe I3C tx/rx buffers Date: Wed, 11 Nov 2026 11:10:32 +0530 Message-ID: <20261111054034.2453874-2-Akshay.Gupta@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261111054034.2453874-1-Akshay.Gupta@amd.com> References: <20261111054034.2453874-1-Akshay.Gupta@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BCD:EE_|PH8PR12MB6844:EE_ X-MS-Office365-Filtering-Correlation-Id: 1866f91f-b082-4540-cdf6-08df3fb65bdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|82310400026|36860700016|10067099003|11063799006|56012099006|261021121427099003|261021123027099003|261026121527099003|261102123227099003|261009223027099003|18002099003|22082099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 93kLok8K/dIMCpK+Dd7Y42CmyvnubuII6g3oRO69PT1bv85Lqak6IrtIXgisVYQj98oNbebvkO+89G4im6fwJj/lZ2f+Es4mM2J7lsVXy9hxqZ5aJoILs7sbQTB8fgDW645HTtrgvYXcvqQfm9yydP/01HFEw7d7x6Yvi49bjAaRjfGkTo+/Ik386zXZ5UqmTUKtJ2yShC37DIkdu1YPv4ke1j0jBzxoLfz/F3ATSSGFOUbTGh1HIUJxAsl/+dj5ZHP+mI40Rj228kx+jabCmcxqDXw1XCDnbIQARUoWzHl7oKWNOd4UgrtSh/nMx2edWeFgp4UOw11AdBvnjqlVSxGgIwAyBPBADlnssa5TflMVBzQxpO272D8mlRr3xRJoYi3N2BY+r+Cy6dQll8HNZw6DSdVfb60ukYZig3UBaMcDubcl4FFl/T2XQAvLdMid X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2026 05:40:56.7274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1866f91f-b082-4540-cdf6-08df3fb65bdc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BCD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6844 From: Prathima Lk This change replaces the open-coded tx[2] array and single-byte scalar rx field in struct sbtsi_i3c_priv with named, sized buffers (SBTSI_TX_LEN and SBTSI_RX_LEN) and makes rx a proper array. The motivation is an upcoming patch adding the SB-TSI Trace Buffer Acquire Interface, which shares the same I3C target core and needs larger buffers. Preparing the sizes now lets that follow-up patch grow the buffers without reworking the struct or register access code. Each buffer stays aligned to ARCH_DMA_MINALIGN for DMA safety on noncoherent platforms. Affected areas are tsi-core.c and tsi-core.h. Tested by building the driver and verifying I3C register reads and writes still function correctly on the target hardware. Signed-off-by: Prathima Lk Signed-off-by: Akshay Gupta --- drivers/misc/amd-sbi/tsi-core.c | 4 ++-- drivers/misc/amd-sbi/tsi-core.h | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/misc/amd-sbi/tsi-core.c b/drivers/misc/amd-sbi/tsi-core.c index 5c178702c67a..1920e4dc7b67 100644 --- a/drivers/misc/amd-sbi/tsi-core.c +++ b/drivers/misc/amd-sbi/tsi-core.c @@ -60,13 +60,13 @@ static int sbtsi_i3c_read(struct sbtsi_data *data, u8 reg, u8 *val) /* Read the data byte into a separate buffer (DMA_FROM_DEVICE). */ xfers[1].rnw = true; xfers[1].len = 1; - xfers[1].data.in = &priv->rx; + xfers[1].data.in = priv->rx; ret = i3c_device_do_xfers(data->i3cdev, xfers, 2, I3C_SDR); if (ret) return ret; - *val = priv->rx; + *val = priv->rx[0]; return ret; } diff --git a/drivers/misc/amd-sbi/tsi-core.h b/drivers/misc/amd-sbi/tsi-core.h index 4cf55c46230e..8efe7e220f4a 100644 --- a/drivers/misc/amd-sbi/tsi-core.h +++ b/drivers/misc/amd-sbi/tsi-core.h @@ -11,6 +11,10 @@ #include #include +/* SB-TSI register access transaction sizes in bytes. */ +#define SBTSI_TX_LEN 2 /* [0] register address, [1] value */ +#define SBTSI_RX_LEN 1 /* single data byte */ + /** * struct sbtsi_i3c_priv - per-device state for I3C SBTSI (includes DMA-safe buffers) * @data: public device state exposed via dev_set_drvdata() @@ -19,8 +23,8 @@ */ struct sbtsi_i3c_priv { struct sbtsi_data data; - u8 tx[2]; - u8 rx __aligned(ARCH_DMA_MINALIGN); + u8 tx[SBTSI_TX_LEN] __aligned(ARCH_DMA_MINALIGN); + u8 rx[SBTSI_RX_LEN] __aligned(ARCH_DMA_MINALIGN); }; int create_misc_tsi_device(struct sbtsi_data *data, struct device *dev); -- 2.34.1