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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by MW1PEPF0001888E.mail.protection.outlook.com (10.167.249.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Wed, 11 Nov 2026 06:45:04 +0000 Received: from BLR-L1-SARUNKOD.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Wed, 11 Nov 2026 00:44:54 -0600 From: Sairaj Kodilkar To: "H. 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Per the AMD IOMMU specification [1] (section 2.2.5.4), with GAPPI enabled the IOMMU delivers a physical APIC interrupt to the CPU described by IRTE[Destination], using IRTE[GATag][7:0] as the vector, while still updating the guest vAPIC backing page IRR as usual. The AMD IOMMU also allows suppressing GAPPI interrupts using the IRTE[GAPPIDis] bit when the GAPPIDisSup feature is available in extended feature register 2. The AMD IOMMU driver sets this bit when the wakeup_intr flag is not set by KVM. Note: amd_iommu_gappi is currently false; a later patch enables it via the kernel command line. [1] https://docs.amd.com/v/u/en-US/48882_3.11_IOMMU_PUB Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 4 +++- drivers/iommu/amd/init.c | 5 +++++ drivers/iommu/amd/iommu.c | 31 +++++++++++++++++++---------- include/linux/amd-iommu.h | 6 ++++++ 4 files changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index f98770db0090..4600674baf84 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -100,6 +100,7 @@ /* Extended Feature 2 Bits */ #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) #define FEATURE_GCR3TRPMODE BIT_ULL(3) +#define FEATURE_GAPPIDISSUP BIT_ULL(4) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) @@ -992,7 +993,8 @@ union irte_ga_lo { no_fault : 1, /* ------ */ ga_log_intr : 1, - rsvd1 : 3, + rsvd1 : 2, + gappi_dis : 1, is_run : 1, /* ------ */ guest_mode : 1, diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 58f63298493b..054ef7262f3c 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -160,6 +160,11 @@ u8 amd_iommu_hpt_vasize; /* Guest page table level */ int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; +#ifdef CONFIG_IRQ_REMAP +bool amd_iommu_gappi; +EXPORT_SYMBOL(amd_iommu_gappi); +#endif + int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c00a85b3a090..3557d6e0d65c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -4063,9 +4063,20 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, APICID_TO_IRTE_DEST_HI(apicid); entry->lo.fields_vapic.is_run = true; entry->lo.fields_vapic.ga_log_intr = false; + entry->lo.fields_vapic.gappi_dis = false; } else { - entry->lo.fields_vapic.is_run = false; - entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + if (amd_iommu_gappi) { + entry->lo.fields_vapic.gappi_dis = !wakeup_intr && + check_feature2(FEATURE_GAPPIDISSUP); + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.destination = + APICID_TO_IRTE_DEST_LO(apicid); + entry->hi.fields.destination = + APICID_TO_IRTE_DEST_HI(apicid); + } else { + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + } } } @@ -4076,15 +4087,15 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, * If the vCPU is scheduled to run on pCPU (@is_running = 1), configure the * Destination with the pCPU's APIC ID, set IsRun, and clear GALogIntr. If the * vCPU is scheduled out (@is_running = 0), clear IsRun and set/clear GALogIntr - * based on input from the caller (e.g. KVM only requests wakeup_intr when the - * vCPU is blocking and requires a notification wake event). This API is - * intended to be used when a vCPU is scheduled in/out (or stops running for - * any reason), to do a fast update of IsRun, GALogIntr, and (conditionally) - * Destination. + * and GAPPIDis based on input from the caller (e.g. KVM only requests + * wakeup_intr when the vCPU is blocking and requires a notification wake + * event). This API is intended to be used when a vCPU is scheduled in/out (or + * stops running for any reason), to do a fast update of IsRun, GALogIntr, + * GAPPIDis and (conditionally) Destination. * - * Per the IOMMU spec, the Destination, IsRun, and GATag fields are not cached - * and thus don't require an invalidation to ensure the IOMMU consumes fresh - * information. + * Per the IOMMU spec, the Destination, IsRun, GATag and GAPPIDis fields are + * not cached and thus don't require an invalidation to ensure the IOMMU + * consumes fresh information. */ int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, bool is_running) { diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 2b340f0f5b31..14be1322b7b6 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -35,6 +35,9 @@ extern int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, extern int amd_iommu_activate_guest_mode(void *data, int apicid); extern int amd_iommu_deactivate_guest_mode(void *data); +/* IOMMU AVIC Flag */ +extern bool amd_iommu_gappi; + #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ static inline int @@ -58,6 +61,9 @@ static inline int amd_iommu_deactivate_guest_mode(void *data) { return 0; } + +#define amd_iommu_gappi false + #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ int amd_iommu_get_num_iommus(void); -- 2.34.1