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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] net: sgi: ioc3-eth: apply the DMA attributes only to 64-bit addresses Date: Wed, 11 Nov 2026 10:51:37 +0100 Message-ID: <20261111095138.1757-2-kaloz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261111095138.1757-1-kaloz@kernel.org> References: <20261111095138.1757-1-kaloz@kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit A Bridge 64-bit direct-mapped DMA address carries the target widget and the DMA attributes. An address in the 2GB 32-bit direct window carries neither, so attributes OR-ed onto one aim it at widget 0, and every receive raises a PCI error. Apply them, and the RX barrier's upper address bits, only to 64-bit addresses. IP27 and IP30 give the IOC3 64-bit addresses; behind an XBridge or PIC it can use the window. Signed-off-by: Imre Kaloz --- Previously posted as 25/53 of the IP35 series v2: https://lore.kernel.org/all/cover.1791890466.git.kaloz@kernel.org/ drivers/net/ethernet/sgi/ioc3-eth.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/sgi/ioc3-eth.c b/drivers/net/ethernet/sgi/ioc3-eth.c index 009f37105eaf..25139cf5ff62 100644 --- a/drivers/net/ethernet/sgi/ioc3-eth.c +++ b/drivers/net/ethernet/sgi/ioc3-eth.c @@ -152,19 +152,37 @@ static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb, } #ifdef CONFIG_PCI_XTALK_BRIDGE +/* A Bridge 64-bit direct-mapped DMA address carries the target widget in + * bits 63:60 and the DMA attributes below it. An address in the 32-bit + * direct window carries neither, so attributes OR-ed onto one form a + * 64-bit address aimed at widget 0. + */ static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) { + if (!(addr & PCI64_ATTR_TARG_MASK)) + return addr; + return (addr & ~PCI64_ATTR_BAR) | attr; } -#define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT) +/* The RX barrier's upper address bits follow the same form. */ +static inline u32 ioc3_erbar(dma_addr_t addr) +{ + if (!(addr & PCI64_ATTR_TARG_MASK)) + return 0; + + return ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT; +} #else static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) { return addr; } -#define ERBAR_VAL 0 +static inline u32 ioc3_erbar(dma_addr_t addr) +{ + return 0; +} #endif static int ioc3eth_nvmem_match(struct device *dev, const void *data) @@ -727,7 +745,7 @@ static void ioc3_init(struct net_device *dev) readl(®s->emcr); /* Misc registers */ - writel(ERBAR_VAL, ®s->erbar); + writel(ioc3_erbar(ip->rxr_dma), ®s->erbar); readl(®s->etcdc); /* Clear on read */ writel(15, ®s->ercsr); /* RX low watermark */ writel(0, ®s->ertr); /* Interrupt immediately */ -- 2.47.3