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[83.150.40.162]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-498363df7a5sm11089358f8f.37.2026.11.11.05.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 05:31:41 -0800 (PST) From: Frank Obergfell To: Shawn Guo , Sascha Hauer , Frank Li , Neil Armstrong , Michael Walle , Dario Binacchi , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Baluta , Jessica Zhang , Fabio Estevam , Pengutronix Kernel Team , Alexander Forsch , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Obergfell Subject: [PATCH v3 2/5] drm/panel: ilitek-ili9806e: Add support for Youritech et050fw01-kt panel Date: Wed, 11 Nov 2026 14:31:16 +0100 Message-ID: <20261111133119.1063210-3-frank.obergfell@bytesatwork.ch> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261111133119.1063210-1-frank.obergfell@bytesatwork.ch> References: <20261111133119.1063210-1-frank.obergfell@bytesatwork.ch> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for the Youritech et050fw01-kt 480x854 MIPI-DSI panel driven by an Ilitek ILI9806E controller. The panel requires 2 MIPI-DSI data lanes, video burst mode, and supplies for vdd (3.3V) and vccio (1.8V). Signed-off-by: Frank Obergfell --- .../drm/panel/panel-ilitek-ili9806e-core.c | 4 +- .../gpu/drm/panel/panel-ilitek-ili9806e-dsi.c | 158 ++++++++++++++++++ 2 files changed, 161 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e-core.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e-core.c index 81d48c402aec..5509af289393 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9806e-core.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e-core.c @@ -91,7 +91,9 @@ int ili9806e_probe(struct device *dev, void *transport, if (of_device_is_compatible(dev->of_node, "densitron,dmt028vghmcmi-1d") || of_device_is_compatible(dev->of_node, - "ortustech,com35h3p70ulc")) { + "ortustech,com35h3p70ulc") || + of_device_is_compatible(dev->of_node, + "youritech,et050fw01-kt")) { ctx->supplies[ctx->num_supplies++].supply = "vccio"; set_prepare_prev_first = true; } diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e-dsi.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e-dsi.c index 89915d58f69d..c1b78700aaa0 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9806e-dsi.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e-dsi.c @@ -464,9 +464,167 @@ static const struct ili9806e_dsi_panel_desc dmt028vghmcmi_1d_desc = { .lanes = 2, }; +static void youritech_et050fw01_kt_init(struct mipi_dsi_multi_context *ctx) +{ + /* Switch to page 1 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10); /* Output SDA */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x00); /* set DE/VSYNC mode */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); /* DE = 1 Active */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01); /* Resolution 480 X 854 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); /* Inversion setting 2-dot */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16); /* BT AVDD, AVDD */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x33); + mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x09); /* SET VGH clamp level */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x06); /* SET VGL clamp level */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x88); /* VREG1 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x88); /* VREG2 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00); /* Flicker MSB */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x49); /* Flicker LSB */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x49); + mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00); + + /* Positive Gamma */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x12); + mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00); + + /* Negative Gamma */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00); + + /* Switch to page 6 (GIP settings) */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98); + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf4); + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xee); + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xff); + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xbb); + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xaa); + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0xdd); + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0xcc); + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x66); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x77); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22); + + /* Switch to page 7 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77); + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0xb2); + + /* Switch to page 0 & set Pixel Format (RGB888 = 0x77) */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x77); +} + +static const struct drm_display_mode youritech_et050fw01_kt_default_mode = { + .clock = 30000, + + .hdisplay = 480, + .hsync_start = 480 + 25, + .hsync_end = 480 + 25 + 10, + .htotal = 480 + 25 + 10 + 125, + + .vdisplay = 854, + .vsync_start = 854 + 20, + .vsync_end = 854 + 20 + 4, + .vtotal = 854 + 20 + 4 + 16, + + .width_mm = 68, + .height_mm = 121, + + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct ili9806e_dsi_panel_desc youritech_et050fw01_kt_desc = { + .init_sequence = youritech_et050fw01_kt_init, + .display_mode = &youritech_et050fw01_kt_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 2, +}; + static const struct of_device_id ili9806e_dsi_of_match[] = { { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc }, { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc }, + { .compatible = "youritech,et050fw01-kt", .data = &youritech_et050fw01_kt_desc }, { } }; MODULE_DEVICE_TABLE(of, ili9806e_dsi_of_match); -- 2.47.3