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Wed, 11 Nov 2026 05:39:34 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba01fea745sm136757365e9.10.2026.11.11.05.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 05:39:33 -0800 (PST) From: Agustin Santiago Isasmendi To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Arnd Bergmann , =?UTF-8?q?Stefan=20D=C3=B6singer?= , Navid Ghahremani , Krzysztof Kozlowski Subject: [PATCH 1/2] ARM: l2c: factor out the number of ways Date: Wed, 11 Nov 2026 14:39:29 +0100 Message-Id: <20261111133930.3665251-2-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20261111133930.3665251-1-isasmendi.agus@gmail.com> References: <20261111133930.3665251-1-isasmendi.agus@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit __l2c_init() derives the number of ways from the cache ID and the auxiliary control register. Move that into l2c_num_ways() so that the next patch can use it before the cache is initialised. No functional change. Assisted-by: LLM Signed-off-by: Agustin Santiago Isasmendi --- arch/arm/mm/cache-l2x0.c | 50 +++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 470867160076..eaa1fb44886e 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -778,6 +778,26 @@ static const struct l2c_init_data l2c310_init_fns __initconst = { }, }; +/* Number of ways, from the cache ID and the auxiliary control register */ +static unsigned int __init l2c_num_ways(u32 cache_id, u32 aux) +{ + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + case L2X0_CACHE_ID_PART_L310: + return aux & L310_AUX_CTRL_ASSOCIATIVITY_16 ? 16 : 8; + + case L2X0_CACHE_ID_PART_L210: + case L2X0_CACHE_ID_PART_L220: + return (aux >> 13) & 0xf; + + case AURORA_CACHE_ID: + return 2 << ((((aux >> 13) & 0xf) + 1) >> 2); + + default: + /* Assume unknown chips have 8 ways */ + return 8; + } +} + static int __init __l2c_init(const struct l2c_init_data *data, u32 aux_val, u32 aux_mask, u32 cache_id, bool nosync) { @@ -809,33 +829,11 @@ static int __init __l2c_init(const struct l2c_init_data *data, pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", old_aux, aux); - /* Determine the number of ways */ - switch (cache_id & L2X0_CACHE_ID_PART_MASK) { - case L2X0_CACHE_ID_PART_L310: - if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) - pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); - if (aux & (1 << 16)) - ways = 16; - else - ways = 8; - break; - - case L2X0_CACHE_ID_PART_L210: - case L2X0_CACHE_ID_PART_L220: - ways = (aux >> 13) & 0xf; - break; - - case AURORA_CACHE_ID: - ways = (aux >> 13) & 0xf; - ways = 2 << ((ways + 1) >> 2); - break; - - default: - /* Assume unknown chips have 8 ways */ - ways = 8; - break; - } + if ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310 && + (aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) + pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); + ways = l2c_num_ways(cache_id, aux); l2x0_way_mask = (1 << ways) - 1; /* -- 2.30.2