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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3751fe2ff5dsm21856793eec.5.2026.11.11.20.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 20:37:07 -0800 (PST) From: Varadarajan Narayanan Date: Thu, 12 Nov 2026 10:06:29 +0530 Subject: [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261112-08-dts-v9-10-c34de4f78fbb@oss.qualcomm.com> References: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> In-Reply-To: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfX0O4jMtzD41Nm 4wdM0TnSTB/MCwQLTnwYQA2Vet/xzN31K1iBgIvSoMpbpNazCKxk3HH1/4/Ss6qyMo3vqzUa31i s4blnZeI1gLJ1ZG32TZne252TbYhvyXUO5mULwWzD/HkuBcA7VMlHIPR+jpGI8pYb6E232ltjJq DDs7ii5gD2UCyYqCT9U77fBZ5N4dly5c4Euz8COW2KZ168LdWCvHi9Eqffw8UYp66KSNwFgfQnx EE3Qei253XrIfeIftFdFKlgJ6ItvRKw3m9z/JYFeqckF2HRn0RT1vZQqOLm6x8jM+kANWTMPzb4 5JiMMBIeQWOKc/doW3uzHRefGlhn5nF0CrRpL/9/SH9/bcj7UbpaXqoQ4cfpY9ufvIkYyFzYRRV QfM83S3VAsdEBuUHn5OjkdYMLr8K0b2/3asyyYpNwKXlXMBLfehQuB8nkNUhy/cVis4Yk8iyDl7 40NZ16paFyN8aE1pLZw== X-Proofpoint-ORIG-GUID: tV5CbcGfhccxob_pxqDMtSumIS8hlqg1 X-Authority-Analysis: v=2.4 cv=FeuiV5+6 c=1 sm=1 tr=0 ts=6af54275 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=ll64UZJxbc1SGzsXvscA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: tV5CbcGfhccxob_pxqDMtSumIS8hlqg1 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfX0GrRFCGcFl+D Kzga8FRgBY5lJnzQ+eEXDMgA2RcSjWoTE4AmO0x9wL8c3zxOGNocFEm5aBVuZe49bzrM1VsOu8Z 4zhekR6/hN+54ai3QZN4dHOL9UnR8a8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120018 Add SPI node definition for the QUP SPI blocks present in IPQ5210. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 36f874e57b42..052c2f3df94d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -181,6 +181,14 @@ opp-32000000 { }; }; + spi_opp_table_50mhz: opp-table-spi50mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -459,6 +467,18 @@ qupv3: geniqup@1ac0000 { #address-cells = <2>; #size-cells = <2>; + spi0: spi@1a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&spi_opp_table_50mhz>; + status = "disabled"; + }; + uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x01a84000 0x0 0x4000>; @@ -495,6 +515,18 @@ i2c1: i2c@1a8c000 { status = "disabled"; }; + spi1: spi@1a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&spi_opp_table_50mhz>; + status = "disabled"; + }; + i2c2: i2c@1a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x01a94000 0x0 0x4000>; -- 2.34.1