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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3751fe2ff5dsm21856793eec.5.2026.11.11.20.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 20:36:34 -0800 (PST) From: Varadarajan Narayanan Date: Thu, 12 Nov 2026 10:06:21 +0530 Subject: [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261112-08-dts-v9-2-c34de4f78fbb@oss.qualcomm.com> References: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> In-Reply-To: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfXwAvEf7kDivdi zRVM88N3/I7BN+Ez/366pz3pfQyoraGY0uT6/D8SD9Ci6DkwPDrP5TVr9RWhwbLKIiJxX8HpY+X 6ntwFll29F4OtJWKoukYmsQQlUYETw0= X-Authority-Analysis: v=2.4 cv=Yrya1IYX c=1 sm=1 tr=0 ts=6af54255 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=sBhH8NEu279NYU_71NoA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: fQHmgOUvBWsR9YlEVNarK7tDE_9aakVm X-Proofpoint-ORIG-GUID: fQHmgOUvBWsR9YlEVNarK7tDE_9aakVm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfX67wMsROojj6C uc1+awVyaaxWoYoca8Aqo4XYm5g5exsqivGmB3JXF9d+gP4MJsf2hRvG30qD/In3WaiMtYYHfhP 4bv1MLSGXtl+Qp1F0a2LkxNWwZVlILcqs5GuTjGSPhRY1E5kqvmr/ntInDqE12ieVcQmULEltuG ThC0uBOPV11iU1cl6ijCQBhZq3CnzKrVrofrxfQVXn+RYi0DXmxc2H9wwUywU7YYu0NvBuvIGU0 i1rB2tSAwjX67EiYCdRlkOdQa3qWdmmBfz9y6TTCIDODqXkCgCHHzraltpaohM8mJ0f+ca1oZL+ pS+A01ww9vkpSlAbmTn8Bj9vw937yQyHEl2zFYRNATxO2M8eHAt4TqQEj8vUNarv5ybRz6IFfx7 9zHCXQRJUsaFhmrfiuXApXMtLnKr1RwoI/ROXFl6qiGPtAT5E4Nbw4+1rbDqugPHefnWBENIPDW BsyN9WRTSjY8hA40+Fg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120018 RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND share the GPIOs. The board has to be reworked to change from EMMC to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi and include it in variant specific DTS file. Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. Signed-off-by: Varadarajan Narayanan --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 225 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 79 +------- 2 files changed, 227 insertions(+), 77 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi new file mode 100644 index 000000000000..6fb8666ffbfd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "ipq5210.dtsi" + +/ { + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + vreg_misc_3p3: regulator-usb-3p3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb_hs_vdda_3p3"; + }; + + vreg_misc_1p8: regulator-usb-1p8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdda_1p8_usb"; + }; + + vreg_misc_0p925: regulator-usb-0p925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdd_core_usb"; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + +&qusb_phy_0 { + vdd-supply = <&vreg_misc_0p925>; + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-dpdm-supply = <&vreg_misc_3p3>; + + status = "okay"; +}; + +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHz. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&ssphy_0 { + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-supply = <&vreg_misc_0p925>; + + status = "okay"; +}; + +&tlmm { + pcie1_default_state: pcie1-default-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + pcie0_default_state: pcie0-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + qpic_snand_default_state: qpic-snand-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs_n"; + drive-strength = <8>; + bias-disable; + }; + + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + }; + + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + + status = "okay"; +}; + +/* + * The frequency of xo_board is fixed to 24 MHz, which is routed + * from WiFi output clock 48 MHz divided by 2. + */ +&xo_board { + clock-div = <2>; + clock-mult = <1>; +}; + +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts index 519307c6b61e..43cdb981a4ba 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -5,30 +5,11 @@ /dts-v1/; -#include "ipq5210.dtsi" +#include "ipq5210-rdp504-common.dtsi" / { - model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504 (eMMC)"; compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -/* - * The bootstrap pins for the board select the XO clock frequency that - * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically - * enables the right dividers, to ensure the reference clock output - * from WiFi to the CMN PLL is 48 MHz. - */ -&ref_48mhz_clk { - clock-div = <1>; - clock-mult = <1>; }; &sdhc { @@ -41,59 +22,3 @@ &sdhc { status = "okay"; }; - -&sleep_clk { - clock-frequency = <32000>; -}; - -&tlmm { - qup_uart1_default_state: qup-uart1-default-state { - pins = "gpio38", "gpio39"; - function = "qup_se1"; - drive-strength = <6>; - bias-pull-down; - }; - - sdhc_default_state: sdhc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; -}; - -&uart1 { - pinctrl-0 = <&qup_uart1_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -/* - * The frequency of xo_board is fixed to 24 MHz, which is routed - * from WiFi output clock 48 MHz divided by 2. - */ -&xo_board { - clock-div = <2>; - clock-mult = <1>; -}; - -&xo_clk { - clock-frequency = <48000000>; -}; -- 2.34.1