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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3751fe2ff5dsm21856793eec.5.2026.11.11.20.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 20:37:03 -0800 (PST) From: Varadarajan Narayanan Date: Thu, 12 Nov 2026 10:06:28 +0530 Subject: [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261112-08-dts-v9-9-c34de4f78fbb@oss.qualcomm.com> References: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> In-Reply-To: <20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfX6IeptTW6L/bn PahtktIaiPtA7JPUr0GLDKPEeXUV82OdHiZOul+/Wb86jdy71JnvbCJ92EEb/4AdOZklyrq/tuH zKLGWpN5BCEU6eK0+b04L+DAo+DYChY= X-Proofpoint-GUID: HQ_bvmSnS3r0yIrnIPoaDY_WA7z3YWe7 X-Proofpoint-ORIG-GUID: HQ_bvmSnS3r0yIrnIPoaDY_WA7z3YWe7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDAxOCBTYWx0ZWRfX4Am0VwGrWDb0 HaXxP3jis0gtCL6e+3Hgtycj6dgGABk++WOLYtvCySH90Uaa6GgMpcsDmxyhQXPyD+uShNTGWfW OYTf357S0ujwpTAgMh/+lCn1BATDuMxkTwD+rMESm8w1NhgpZ8JHVgFjhlqSn0cDO56re/neY8Z /NYOr0g4N+00KD/NnIzZ6Xcb10wRwyWsykgAnsPLMskIjzzEtPDAOH3HEptypK2PtARva0K3Emc Nh57vaoFTcPlLE778mwY2JvVrTFvvMlAL/6h9Tsx5n8bwj9b5M+2NYK6PDXz3yB7Bmlmco9wzTl fNmIlsKCw7r2w/+5DN0a27wmrapHelmQ1ZvJce2pIuP6AOFc12wtmfo8FSb8HXdEr686XvBs+af MGl26Dr7YcOHo6HtcNmRRCTIsb8dKscr5sOvarJXClCzLocrmrFeBDVQgbs4ia8qm7fASqzeOc7 YDnKZeCEKHzj/j5SDhQ== X-Authority-Analysis: v=2.4 cv=LvcHWXdc c=1 sm=1 tr=0 ts=6af54271 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=GVWKzDYot3hTMZ8E5o4A:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120018 Add the QUPv3 I2C controller nodes for IPQ5210 and enable I2C0 with the required pin configuration on RDP504. Signed-off-by: Varadarajan Narayanan --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 87a7e625a2a4..7cbdcf58d946 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -59,6 +59,13 @@ vreg_misc_0p925: regulator-usb-0p925 { }; }; +&i2c0 { + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -202,6 +209,15 @@ clock-pins { }; }; + qup_i2c0_default: qup-i2c0-default-state { + qup-i2c0-pins { + pins = "gpio20", "gpio21"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-up; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins = "gpio38", "gpio39"; function = "qup_se1"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 4cb9f399d480..36f874e57b42 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -173,6 +173,14 @@ opp-300000000 { }; }; + i2c_opp_table_32mhz: opp-table-qup32mhz { + compatible = "operating-points-v2"; + + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -460,6 +468,45 @@ uart1: serial@1a84000 { status = "disabled"; }; + + i2c0: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c2: i2c@1a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { -- 2.34.1