[PATCH v2 2/2] gpu: nova-core: gsp: cmdq: increase MSGQ_NUM_PAGES to 64

[Eliot Courtney <ecourtney@nvidia.com>]

In the msgq v2 protocol, which the r000 firmware uses, the queue
pointers are kept in u32 registers and increase monotonically until they
wrap at 2^32.

`MSGQ_NUM_PAGES` is currently 63 and does not divide 2^32. This means
that on msgq v2, the slot can jump backwards when the counters wrap.
For example:

    (2^32 - 2) % 63 == 2
    (2^32 - 1) % 63 == 3
             0 % 63 == 0    (slot 0 instead of slot 4)

The writer can then overwrite slots before the reader has read them.

Increase `MSGQ_NUM_PAGES` to 64 and check at compile time that
`MSGQ_NUM_PAGES` divides 2^32.

Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
---
 drivers/gpu/nova-core/gsp/cmdq.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index 33074bb53e8c..8d34acaef9ea 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -84,7 +84,12 @@ trait CommandElement {
 }
 
 /// Number of GSP pages making the [`Msgq`].
-pub(crate) const MSGQ_NUM_PAGES: u32 = 0x3f;
+pub(crate) const MSGQ_NUM_PAGES: u32 = 64;
+
+// The queue pointers are wrapping `u32` counters, and the slot is
+// `counter % MSGQ_NUM_PAGES`. For slots to remain contiguous when a counter
+// wraps, `MSGQ_NUM_PAGES` must divide `1 << 32`.
+static_assert!((1u64 << u32::BITS) % cv!(MSGQ_NUM_PAGES => u64) == 0);
 
 /// Circular buffer of a [`Msgq`].
 ///

-- 
2.56.0